资源列表
[VHDL编程] adc_interface-master
说明:adc with fpga serial data transmission miso,mosi,cs,sclk<subhash > 在 2025-06-28 上传 | 大小:27kb | 下载:0
[VHDL编程] add
说明:一个用quartus原理图输入的全加器,(A full adder with quartus schematic input,)<zhangning194 > 在 2025-06-28 上传 | 大小:1kb | 下载:0
[VHDL编程] uart
说明:实现与电脑端串行数据发送与接收,波特率为9600(Realize serial data sending and receiving with the computer terminal)<hurricanhup > 在 2025-06-28 上传 | 大小:1kb | 下载:0
[VHDL编程] spram
说明:verilog编写的spram,包含顶层模块,控制模块和spram本体,其中spram为Altera提供的ip核,已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)<keykai > 在 2025-06-28 上传 | 大小:2.73mb | 下载:0
[VHDL编程] bist 2017 paper
说明:A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi<Maddy619 > 在 2025-06-28 上传 | 大小:1.5mb | 下载:0
[VHDL编程] tengkan-V2.2
说明:Calculation crosshairs diffraction image at different distances, Channelized receiver based on multi-phase structure, Verification is available.<manjaofienen > 在 2025-06-28 上传 | 大小:148kb | 下载:0