资源列表
[VHDL编程] soft_demapper
说明:This is soft demapper algorithm<sunghwanchoi> 在 2025-06-14 上传 | 大小:9kb | 下载:0
[VHDL编程] source
说明:本源码是 基于VERILOG的SDRAM的开发与实现 并能实现 刷新,预充电,突发长度为8字节等功能 已验证,可用-The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available<zhao> 在 2025-06-14 上传 | 大小:9kb | 下载:0
[VHDL编程] NominaltoBinary
说明:this vi is used specially in fpga targets to convert nominal raw material to binary<habal> 在 2025-06-14 上传 | 大小:9kb | 下载:0
[VHDL编程] SpiMaster
说明:This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an<RutaliMulye> 在 2025-06-14 上传 | 大小:9kb | 下载:0
[VHDL编程] Template_Slave
说明:avalon总线的从端口实例代码,简单,易懂,方便初学者学习。-avalon bus example code from the port, simple, easy to understand, easy for beginners to learn.<穆屹峰> 在 2025-06-14 上传 | 大小:9kb | 下载:0