资源列表
[VHDL编程] VHDL-design-methedology
说明:VHDL design methedology<Anojhkumaran> 在 2025-08-02 上传 | 大小:42kb | 下载:1
[VHDL编程] Verilog
说明:设计一个自动售货机,此机能出售1元、2元、5元、10元的四种商品。用于modelsim verilog 语言的编写-To design a vending machine, this function is the sale of 1 yuan, 2 yuan, 5 yuan, 10 yuan of the four commodities. The sale of what kind of goods to the customer pressing a button and digital<guzhou> 在 2025-08-02 上传 | 大小:42kb | 下载:0
[VHDL编程] hsk4571_cuankou
说明:串口通信SCI VHDL实现,在QUATTUS||9.0下编写,可在9.0及以上版本运行并下载,芯片为Altera的Cyclone3 EP3C8T1-Serial communication SCI VHDL realize, in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for Altera' s Cyclone3 EP3C8T144<hongsk> 在 2025-08-02 上传 | 大小:42kb | 下载:0
[VHDL编程] display
说明:seven segment display apllication with only one push button up counter<resul koksal> 在 2025-08-02 上传 | 大小:42kb | 下载:0
[VHDL编程] dac_900
说明:DAC900芯片驱动的Verilog语言描述,亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用,也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.<唐宏伟> 在 2025-08-02 上传 | 大小:42kb | 下载:0
[VHDL编程] Han-carlson.ppt
说明:Abstract—Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time,<preethi/charu> 在 2025-08-02 上传 | 大小:42kb | 下载:0