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[VHDL编程] test12
说明:自己用VerilogHDL语言编写的时钟程序,包括时钟进位计数模块,数码管显示模块和闹钟模块。在cpld芯片上经测试有效(开发环境没找到VerilogHDL,就选了VHDL,其实他们不一样的……)-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te<潘昕> 在 2025-06-08 上传 | 大小:1kb | 下载:0
[VHDL编程] randomizervhdl
说明:Randomizer Vhdl he RTL now is working correctly, and the TB also is working but there is a problem in the sequence of the reset and and the load<amrnour> 在 2025-06-08 上传 | 大小:1kb | 下载:0
[VHDL编程] decoder_using_with
说明:decoder_using_with verilog code<amin> 在 2025-06-08 上传 | 大小:1kb | 下载:0