资源列表
[VHDL编程] FPGAshilier
说明:各种fpga的开发资料,非常适用,实在是难得的资料,对于初学者非常有帮助-The development of a variety of FPGA information, very useful, it is hard to come by the information very helpful for beginners<liwen> 在 2025-06-17 上传 | 大小:2.31mb | 下载:0
[VHDL编程] ASI_IN1_and_ASI_OUT1
说明:这是对于从卫星接收下来的TS流,有两路流,对其选择,其中包括同步模块,PCR校正模块,码率调整模块-This is received from the satellite down for the TS stream, there are two streams of their choice, including the synchronization module, PCR correction module, rate adjustment module<庄敏敏> 在 2025-06-17 上传 | 大小:2.31mb | 下载:0
[VHDL编程] TX
说明:In data transmission and telecommunication, bit stuffing (also known—uncommonly—as positive justification) is the insertion of noninformation bits into data. Stuffed bits should not be confused with overhead bits. Bit stuffing is used for variou<lep> 在 2025-06-17 上传 | 大小:2.32mb | 下载:0
[VHDL编程] Cadence-Encounter
说明:8x8 mulitplier. created this file using the midelsim softwre. Tested and simulated. Great waveform, so the testbench is included also. Does anybody knkow how to make a 16x16 arrray multiplier?<rell> 在 2025-06-17 上传 | 大小:2.31mb | 下载:0
[VHDL编程] 5.1-PCF8563
说明:基于pcf8563的数字钟设计,erilog语言编写,以调试-digital clock based on erilog langrage<万云> 在 2025-06-17 上传 | 大小:2.31mb | 下载:0
[VHDL编程] VHDL
说明:数字电路实验程序代码打包下载 版本 宁波大学学年数字电路实验 VHDl编程 部分 -Digital circuit experiment program code package download version Ningbo University academic year programming section VHDl digital circuit experiment<mengchenyezi> 在 2025-06-17 上传 | 大小:2.31mb | 下载:0