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[图形图象] vga_timing_gen
说明:verilog文件 实现VGA时序驱动,产生vsync和hsync信号。附有自检测程序。-Verilog file to achieve VGA timing-driven, resulting in VSYNC and HSYNC signals. With self-testing procedures.<asacoup> 在 2025-11-24 上传 | 大小:4kb | 下载:0
[图形图象] videoldws
说明:本程序在视频流中检测道路线标记,并强调该车辆的行驶线。这些信息可以被用来检测车辆的意外离开并发出警告。-This demo detects road lane markers in a video stream and highlights the lane in which the vehicle is driven. This information can be used to detect an unintended departure from the lane and issue a<swithPr> 在 2025-11-24 上传 | 大小:4kb | 下载:0