文件名称:Vfirr_using__e
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一种基于verilog的fiir滤波，并带matlab仿真
-Based verilog fiir filter with matlab simulation
-Based verilog fiir filter with matlab simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Vfirr_using__e\fir_using_FPGA\adder.v
..............\..............\basic_fir.m
..............\..............\Basic_FIR.v
..............\..............\coeff_0_7.mif
..............\..............\coeff_1_6.mif
..............\..............\coeff_2_5.mif
..............\..............\coeff_3_4.mif
..............\..............\coeff_rom_0_7.v
..............\..............\coeff_rom_1_6.v
..............\..............\coeff_rom_2_5.v
..............\..............\coeff_rom_3_4.v
..............\..............\db\fir.db_info
..............\..............\..\fir.eco.cdb
..............\..............\..\fir.sld_design_entry.sci
..............\..............\fir.qpf
..............\..............\fir.qsf
..............\..............\fir.qws
..............\..............\impulse.vwf
..............\..............\mult_add.v
..............\..............\random.vwf
..............\..............\step.vwf
..............\..............\db
..............\fir_using_FPGA
Vfirr_using__e
..............\..............\basic_fir.m
..............\..............\Basic_FIR.v
..............\..............\coeff_0_7.mif
..............\..............\coeff_1_6.mif
..............\..............\coeff_2_5.mif
..............\..............\coeff_3_4.mif
..............\..............\coeff_rom_0_7.v
..............\..............\coeff_rom_1_6.v
..............\..............\coeff_rom_2_5.v
..............\..............\coeff_rom_3_4.v
..............\..............\db\fir.db_info
..............\..............\..\fir.eco.cdb
..............\..............\..\fir.sld_design_entry.sci
..............\..............\fir.qpf
..............\..............\fir.qsf
..............\..............\fir.qws
..............\..............\impulse.vwf
..............\..............\mult_add.v
..............\..............\random.vwf
..............\..............\step.vwf
..............\..............\db
..............\fir_using_FPGA
Vfirr_using__e