文件名称:mux_4_to_1
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基于verilog的四选一的设计，附带testbench，并且测试通过-Based on the four design in verilog, incidental testbench, and the test passes
(系统自动生成,下载前可以参看下载内容)
下载文件列表
mux_4_to_1\db\logic_util_heursitic.dat
..........\..\mux_4_to_1.cbx.xml
..........\..\mux_4_to_1.cmp.rdb
..........\..\mux_4_to_1.cmp_merge.kpt
..........\..\mux_4_to_1.db_info
..........\..\mux_4_to_1.hier_info
..........\..\mux_4_to_1.hif
..........\..\mux_4_to_1.lpc.html
..........\..\mux_4_to_1.lpc.rdb
..........\..\mux_4_to_1.lpc.txt
..........\..\mux_4_to_1.map.bpm
..........\..\mux_4_to_1.map.cdb
..........\..\mux_4_to_1.map.hdb
..........\..\mux_4_to_1.map.kpt
..........\..\mux_4_to_1.map.logdb
..........\..\mux_4_to_1.map.qmsg
..........\..\mux_4_to_1.map_bb.cdb
..........\..\mux_4_to_1.map_bb.hdb
..........\..\mux_4_to_1.map_bb.logdb
..........\..\mux_4_to_1.pre_map.cdb
..........\..\mux_4_to_1.pre_map.hdb
..........\..\mux_4_to_1.rtlv.hdb
..........\..\mux_4_to_1.rtlv_sg.cdb
..........\..\mux_4_to_1.rtlv_sg_swap.cdb
..........\..\mux_4_to_1.sgdiff.cdb
..........\..\mux_4_to_1.sgdiff.hdb
..........\..\mux_4_to_1.sld_design_entry.sci
..........\..\mux_4_to_1.sld_design_entry_dsc.sci
..........\..\mux_4_to_1.smart_action.txt
..........\..\mux_4_to_1.syn_hier_info
..........\..\mux_4_to_1.tis_db_list.ddb
..........\..\prev_cmp_mux_4_to_1.qmsg
..........\db
..........\incremental_db\compiled_partitions\mux_4_to_1.db_info
..........\..............\...................\mux_4_to_1.root_partition.map.cdb
..........\..............\...................\mux_4_to_1.root_partition.map.dpi
..........\..............\...................\mux_4_to_1.root_partition.map.hbdb.cdb
..........\..............\...................\mux_4_to_1.root_partition.map.hbdb.hb_info
..........\..............\...................\mux_4_to_1.root_partition.map.hbdb.hdb
..........\..............\...................\mux_4_to_1.root_partition.map.hbdb.sig
..........\..............\...................\mux_4_to_1.root_partition.map.hdb
..........\..............\...................\mux_4_to_1.root_partition.map.kpt
..........\..............\compiled_partitions
..........\..............\README
..........\incremental_db
..........\mux_4_to_1.done
..........\mux_4_to_1.flow.rpt
..........\mux_4_to_1.map.rpt
..........\mux_4_to_1.map.summary
..........\mux_4_to_1.qpf
..........\mux_4_to_1.qsf
..........\mux_4_to_1.vhd
..........\mux_4_to_1.vhd.bak
..........\mux_4_to_1_nativelink_simulation.rpt
..........\mux_4_to_1_tb.vhd
..........\mux_4_to_1_tb.vhd.bak
..........\simulation\modelsim\modelsim.ini
..........\..........\........\msim_transcript
..........\..........\........\mux_4_to_1_run_msim_rtl_vhdl.do
..........\..........\........\rtl_work\mux_4_to_1\behav.dat
..........\..........\........\........\..........\behav.dbs
..........\..........\........\........\..........\behav.prw
..........\..........\........\........\..........\behav.psm
..........\..........\........\........\..........\_primary.dat
..........\..........\........\........\..........\_primary.dbs
..........\..........\........\........\mux_4_to_1
..........\..........\........\........\.........._tb\behav.dat
..........\..........\........\........\.............\behav.dbs
..........\..........\........\........\.............\behav.prw
..........\..........\........\........\.............\behav.psm
..........\..........\........\........\.............\_primary.dat
..........\..........\........\........\.............\_primary.dbs
..........\..........\........\........\mux_4_to_1_tb
..........\..........\........\........\_info
..........\..........\........\........\_temp
..........\..........\........\........\_vmake
..........\..........\........\rtl_work
..........\..........\........\vsim.wlf
..........\..........\modelsim
..........\simulation
mux_4_to_1