文件名称:digitalclock_demo
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
该程序适用于xilinx公司的FPGA开发板，spartan3E系列250型号 通过verilog编程实现数字钟的功能，下板子验证可用！-This procedure applies to xilinx FPGA development board Series 250 Model spartan3E digital clock verilog programming under the board to verify available!
(系统自动生成,下载前可以参看下载内容)
下载文件列表
digitalclock_demo
.................\digitalclock.gise
.................\digitalclock.ucf
.................\digitalclock.xise
.................\digitalclock_clkdiv.v
.................\digitalclock_control.v
.................\digitalclock_decoder.v
.................\digitalclock_timer.v
.................\ditigalclock.bgn
.................\ditigalclock.bit
.................\ditigalclock.bld
.................\ditigalclock.cmd_log
.................\ditigalclock.drc
.................\ditigalclock.lso
.................\ditigalclock.ncd
.................\ditigalclock.ngc
.................\ditigalclock.ngd
.................\ditigalclock.ngr
.................\ditigalclock.pad
.................\ditigalclock.par
.................\ditigalclock.pcf
.................\ditigalclock.prj
.................\ditigalclock.ptwx
.................\ditigalclock.stx
.................\ditigalclock.syr
.................\ditigalclock.twr
.................\ditigalclock.twx
.................\ditigalclock.unroutes
.................\ditigalclock.ut
.................\ditigalclock.v
.................\ditigalclock.xpi
.................\ditigalclock.xst
.................\ditigalclock_bitgen.xwbt
.................\ditigalclock_envsettings.html
.................\ditigalclock_guide.ncd
.................\ditigalclock_map.map
.................\ditigalclock_map.mrp
.................\ditigalclock_map.ncd
.................\ditigalclock_map.ngm
.................\ditigalclock_map.xrpt
.................\ditigalclock_ngdbuild.xrpt
.................\ditigalclock_pad.csv
.................\ditigalclock_pad.txt
.................\ditigalclock_par.xrpt
.................\ditigalclock_summary.html
.................\ditigalclock_summary.xml
.................\ditigalclock_usage.xml
.................\ditigalclock_xst.xrpt
.................\divclk.v
.................\iseconfig
.................\.........\digitalclock.projectmgr
.................\.........\ditigalclock.xreport
.................\usage_statistics_webtalk.html
.................\webtalk.log
.................\webtalk_pn.xml
.................\xlnx_auto_0_xdb
.................\...............\cst.xbcd
.................\xst
.................\...\dump.xst
.................\...\........\ditigalclock.prj
.................\...\........\................\ngx
.................\...\........\................\...\notopt
.................\...\........\................\...\opt
.................\...\projnav.tmp
.................\...\work
.................\...\....\hdllib.ref
.................\...\....\vlg02
.................\...\....\.....\ditigalclock.bin
.................\...\....\vlg2E
.................\...\....\.....\control__digitalclock.bin
.................\...\....\vlg3E
.................\...\....\.....\clkdiv__digitalclock.bin
.................\...\....\vlg5D
.................\...\....\.....\divclk.bin
.................\...\....\vlg63
.................\...\....\.....\decoder__digitalclock.bin
.................\...\....\vlg76
.................\...\....\.....\timer__digitalclock.bin
.................\_ngo
.................\....\netlist.lst
.................\_xmsgs
.................\......\bitgen.xmsgs
.................\......\map.xmsgs
.................\......\ngdbuild.xmsgs
.................\......\par.xmsgs
.................\......\pn_parser.xmsgs
.................\......\trce.xmsgs
.................\......\xst.xmsgs