压缩包 : 77433627veriloghdl_advanced_digital_design_code_ch6.rar 列表
VerilogHDL_advanced_digital_design_code_Ch6\ADDVB_Models_6.doc
VerilogHDL_advanced_digital_design_code_Ch6\Add_Accum_1.v
VerilogHDL_advanced_digital_design_code_Ch6\Add_Accum_2.v
VerilogHDL_advanced_digital_design_code_Ch6\Add_Accum_both.v
VerilogHDL_advanced_digital_design_code_Ch6\alu_with_z1.v
VerilogHDL_advanced_digital_design_code_Ch6\badd_4.v
VerilogHDL_advanced_digital_design_code_Ch6\BCD_to_Excess_3a.v
VerilogHDL_advanced_digital_design_code_Ch6\BCD_to_Excess_3b.v
VerilogHDL_advanced_digital_design_code_Ch6\BCD_to_Excess_3b_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\BCD_to_Excess_3c.v
VerilogHDL_advanced_digital_design_code_Ch6\BCD_to_Excess_3c_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\Bi_dir_bus.v
VerilogHDL_advanced_digital_design_code_Ch6\boole_opt.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_a.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_b.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_b0.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_b1.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_b2.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_c.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_d.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_IMP.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_SD.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_SD_0.v
VerilogHDL_advanced_digital_design_code_Ch6\count_ones_SM.v
VerilogHDL_advanced_digital_design_code_Ch6\D_reg4_a.v
VerilogHDL_advanced_digital_design_code_Ch6\expression_sub.v
VerilogHDL_advanced_digital_design_code_Ch6\expression_sub_nb.v
VerilogHDL_advanced_digital_design_code_Ch6\for_and_loop_comb.v
VerilogHDL_advanced_digital_design_code_Ch6\Latched_Seven_Seg_Display.v
VerilogHDL_advanced_digital_design_code_Ch6\latch_if1.v
VerilogHDL_advanced_digital_design_code_Ch6\latch_if2.v
VerilogHDL_advanced_digital_design_code_Ch6\multiple_reg_assign.v
VerilogHDL_advanced_digital_design_code_Ch6\mux_4pri.v
VerilogHDL_advanced_digital_design_code_Ch6\mux_latch.v
VerilogHDL_advanced_digital_design_code_Ch6\mux_logic.v
VerilogHDL_advanced_digital_design_code_Ch6\mux_reg.v
VerilogHDL_advanced_digital_design_code_Ch6\NRZI.v
VerilogHDL_advanced_digital_design_code_Ch6\NRZ_2_Manchester_Mealy.v
VerilogHDL_advanced_digital_design_code_Ch6\NRZ_2_Manchester_Mealy_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\NRZ_2_Manchester_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\NRZ_2_Manchester_Moore_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\operator_group.v
VerilogHDL_advanced_digital_design_code_Ch6\or4_behav.v
VerilogHDL_advanced_digital_design_code_Ch6\or4_behav_latch.v
VerilogHDL_advanced_digital_design_code_Ch6\or_nand.v
VerilogHDL_advanced_digital_design_code_Ch6\res_share.v
VerilogHDL_advanced_digital_design_code_Ch6\ripple_counter.v
VerilogHDL_advanced_digital_design_code_Ch6\Seq_Rec_3_1s.v
VerilogHDL_advanced_digital_design_code_Ch6\Seq_Rec_3_1s_Mealy.v
VerilogHDL_advanced_digital_design_code_Ch6\Seq_Rec_3_1s_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\Seq_Rec_3_1s_Shft_Reg.v
VerilogHDL_advanced_digital_design_code_Ch6\Seq_Rec_Moore_imp.v
VerilogHDL_advanced_digital_design_code_Ch6\shifter_1.v
VerilogHDL_advanced_digital_design_code_Ch6\shifter_2.v
VerilogHDL_advanced_digital_design_code_Ch6\swap_synch.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_a.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_b.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_c.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_d.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_IMP.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_SD.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_SD_0.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_count_ones_SM.v
VerilogHDL_advanced_digital_design_code_Ch6\test_NRZ_2_Manchester_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\Test_Seq_Rec_Moore_imp.v
VerilogHDL_advanced_digital_design_code_Ch6\t_BCD_Excess_3.v
VerilogHDL_advanced_digital_design_code_Ch6\Uni_dir_bus.v.doc
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\ADDVB_Models_6.doc
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Add_Accum_1.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Add_Accum_2.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Add_Accum_both.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\alu_with_z1.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\badd_4.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\BCD_to_Excess_3a.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\BCD_to_Excess_3b.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\BCD_to_Excess_3b_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\BCD_to_Excess_3c.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\BCD_to_Excess_3c_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Bi_dir_bus.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\boole_opt.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_a.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_b.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_b0.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_b1.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_b2.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_c.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_d.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_IMP.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_SD.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\count_ones_SM.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\D_reg4_a.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\expression_sub.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\expression_sub_nb.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\for_and_loop_comb.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Latched_Seven_Seg_Display.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\latch_if1.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\latch_if2.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\multiple_reg_assign.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\mux_4pri.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\mux_latch.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\mux_logic.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\mux_reg.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\NRZI.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\NRZ_2_Manchester_Mealy.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\NRZ_2_Manchester_Mealy_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\NRZ_2_Manchester_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\NRZ_2_Manchester_Moore_Post.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\operator_group.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\or4_behav.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\or4_behav_latch.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\or_nand.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\res_share.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\ripple_counter.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Seq_Rec_3_1s.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Seq_Rec_3_1s_Mealy.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Seq_Rec_3_1s_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Seq_Rec_3_1s_Shft_Reg.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Seq_Rec_Moore_imp.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\shifter_1.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\shifter_2.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\swap_synch.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_a.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_b.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_c.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_d.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_IMP.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_SD.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_count_ones_SM.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\test_NRZ_2_Manchester_Moore.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Test_Seq_Rec_Moore_imp.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\t_BCD_Excess_3.v
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf\Uni_dir_bus.v.doc
VerilogHDL_advanced_digital_design_code_Ch6\_vti_cnf
VerilogHDL_advanced_digital_design_code_Ch6