文件名称:exp_proje
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下载文件列表
project_2\adder.v
.........\design_1\design_1.bd
.........\........\design_1.bxml
.........\........\ip\design_1_axi_ethernetlite_0_0\design_1_axi_ethernetlite_0_0.xci
.........\........\..\.............................\design_1_axi_ethernetlite_0_0.xml
.........\........\..\.........c_addsub_0_0\design_1_c_addsub_0_0.xci
.........\........\..\.....................\design_1_c_addsub_0_0.xml
.........\........\..\...........shift_ram_0_0\design_1_c_shift_ram_0_0.xci
.........\........\..\........................\design_1_c_shift_ram_0_0.xml
.........\........\..\.........jtag_axi_0_0\design_1_jtag_axi_0_0.xci
.........\........\..\.....................\design_1_jtag_axi_0_0.xml
.........\........\..\.........pcie_7x_0_0\design_1_pcie_7x_0_0.xci
.........\........\..\....................\design_1_pcie_7x_0_0.xml
.........\........\..\...................1\design_1_pcie_7x_0_1.xci
.........\........\..\....................\design_1_pcie_7x_0_1.xml
.........\........\..\.........tcc_decoder_3gppmm_0_0\design_1_tcc_decoder_3gppmm_0_0.xci
.........\........\..\...............................\design_1_tcc_decoder_3gppmm_0_0.xml
.........\........\..\.............encoder_3gpp_0_0\design_1_tcc_encoder_3gpp_0_0.xci
.........\........\..\.............................\design_1_tcc_encoder_3gpp_0_0.xml
.........\........\ui\bd_1f5defd0.ui
.........\Nexys4_Master.xdc
.........\project_2.cache\wt\java_command_handlers.wdf
.........\...............\..\webtalk_pa.xml
.........\project_2.xpr
.........\sch.v
.........\simulate.v
.........\design_1\ip\design_1_axi_ethernetlite_0_0
.........\........\..\design_1_c_addsub_0_0
.........\........\..\design_1_c_shift_ram_0_0
.........\........\..\design_1_jtag_axi_0_0
.........\........\..\design_1_pcie_7x_0_0
.........\........\..\design_1_pcie_7x_0_1
.........\........\..\design_1_tcc_decoder_3gppmm_0_0
.........\........\..\design_1_tcc_encoder_3gpp_0_0
.........\........\ip
.........\........\ui
.........\project_2.cache\compile_simlib
.........\...............\wt
.........\design_1
.........\project_2.cache
project_2