文件名称:CPU_Design
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基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
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下载文件列表
CPU_Design
..........\ACC.bsf
..........\ACC.vhd
..........\ACC.vhd.bak
..........\ALU.bsf
..........\ALU.vhd
..........\ALU.vhd.bak
..........\BR.bsf
..........\BR.vhd
..........\BR.vhd.bak
..........\CAR.bsf
..........\CAR.vhd
..........\CAR.vhd.bak
..........\CBR.bsf
..........\CBR.vhd
..........\CBR.vhd.bak
..........\CPU.asm.rpt
..........\CPU.done
..........\CPU.fit.rpt
..........\CPU.fit.smsg
..........\CPU.fit.summary
..........\CPU.flow.rpt
..........\CPU.map.rpt
..........\CPU.map.summary
..........\CPU.pin
..........\CPU.pof
..........\CPU.qpf
..........\CPU.qsf
..........\CPU.qws
..........\CPU.sim.rpt
..........\CPU.sof
..........\CPU.tan.rpt
..........\CPU.tan.summary
..........\CPU_assignment_defaults.qdf
..........\CPU_test.bdf
..........\CPU_test.vwf
..........\db
..........\..\altsyncram_74c1.tdf
..........\..\altsyncram_a3c1.tdf
..........\..\altsyncram_avb1.tdf
..........\..\altsyncram_js61.tdf
..........\..\altsyncram_jub1.tdf
..........\..\altsyncram_ovb1.tdf
..........\..\CPU.asm.qmsg
..........\..\CPU.asm.rdb
..........\..\CPU.asm_labs.ddb
..........\..\CPU.cbx.xml
..........\..\CPU.cmp.bpm
..........\..\CPU.cmp.cdb
..........\..\CPU.cmp.ecobp
..........\..\CPU.cmp.hdb
..........\..\CPU.cmp.kpt
..........\..\CPU.cmp.logdb
..........\..\CPU.cmp.rdb
..........\..\CPU.cmp.tdb
..........\..\CPU.cmp0.ddb
..........\..\CPU.cmp_merge.kpt
..........\..\CPU.db_info
..........\..\CPU.eco.cdb
..........\..\CPU.eds_overflow
..........\..\CPU.fit.qmsg
..........\..\CPU.fnsim.cdb
..........\..\CPU.fnsim.hdb
..........\..\CPU.fnsim.qmsg
..........\..\CPU.hier_info
..........\..\CPU.hif
..........\..\CPU.lpc.html
..........\..\CPU.lpc.rdb
..........\..\CPU.lpc.txt
..........\..\CPU.map.bpm
..........\..\CPU.map.cdb
..........\..\CPU.map.ecobp
..........\..\CPU.map.hdb
..........\..\CPU.map.kpt
..........\..\CPU.map.logdb
..........\..\CPU.map.qmsg
..........\..\CPU.map_bb.cdb
..........\..\CPU.map_bb.hdb
..........\..\CPU.map_bb.logdb
..........\..\CPU.pre_map.cdb
..........\..\CPU.pre_map.hdb
..........\..\CPU.rtlv.hdb
..........\..\CPU.rtlv_sg.cdb
..........\..\CPU.rtlv_sg_swap.cdb
..........\..\CPU.sgdiff.cdb
..........\..\CPU.sgdiff.hdb
..........\..\CPU.sim.cvwf
..........\..\CPU.sim.hdb
..........\..\CPU.sim.qmsg
..........\..\CPU.sim.rdb
..........\..\CPU.simfam
..........\..\CPU.sld_design_entry.sci
..........\..\CPU.sld_design_entry_dsc.sci
..........\..\CPU.smart_action.txt
..........\..\CPU.syn_hier_info
..........\..\CPU.tan.qmsg
..........\..\CPU.tis_db_list.ddb
..........\..\logic_util_heursitic.dat
..........\..\mult_b011.tdf
..........\..\mult_n9t.tdf