文件名称:shuzhishizhong
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数字时钟的verilog程序,课程设计，数字电子技术实验，VHDL-VHDL Verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
绋嬪簭
......\2014111272.asm.rpt
......\2014111272.bdf
......\2014111272.done
......\2014111272.dpf
......\2014111272.fit.rpt
......\2014111272.fit.smsg
......\2014111272.fit.summary
......\2014111272.flow.rpt
......\2014111272.map.rpt
......\2014111272.map.smsg
......\2014111272.map.summary
......\2014111272.pin
......\2014111272.pof
......\2014111272.qpf
......\2014111272.qsf
......\2014111272.qws
......\2014111272.sim.rpt
......\2014111272.sof
......\2014111272.tan.rpt
......\2014111272.tan.summary
......\2014111272.vwf
......\21selector.v.bak
......\alarm.bsf
......\alarm.v
......\alarm.v.bak
......\counter10.bsf
......\counter10.v
......\counter10.v.bak
......\counter24.bsf
......\counter24.v
......\counter24.v.bak
......\counter6.bsf
......\counter6.v
......\counter6.v.bak
......\db
......\..\2014111272.ace_cmp.bpm
......\..\2014111272.ace_cmp.cdb
......\..\2014111272.ace_cmp.ecobp
......\..\2014111272.ace_cmp.hdb
......\..\2014111272.asm.qmsg
......\..\2014111272.cbx.xml
......\..\2014111272.cmp.bpm
......\..\2014111272.cmp.cdb
......\..\2014111272.cmp.ecobp
......\..\2014111272.cmp.hdb
......\..\2014111272.cmp.kpt
......\..\2014111272.cmp.logdb
......\..\2014111272.cmp.rdb
......\..\2014111272.cmp.tdb
......\..\2014111272.cmp0.ddb
......\..\2014111272.cmp2.ddb
......\..\2014111272.cmp_merge.kpt
......\..\2014111272.db_info
......\..\2014111272.eco.cdb
......\..\2014111272.fit.qmsg
......\..\2014111272.hier_info
......\..\2014111272.hif
......\..\2014111272.lpc.html
......\..\2014111272.lpc.rdb
......\..\2014111272.lpc.txt
......\..\2014111272.map.bpm
......\..\2014111272.map.cdb
......\..\2014111272.map.ecobp
......\..\2014111272.map.hdb
......\..\2014111272.map.kpt
......\..\2014111272.map.logdb
......\..\2014111272.map.qmsg
......\..\2014111272.map_bb.cdb
......\..\2014111272.map_bb.hdb
......\..\2014111272.map_bb.logdb
......\..\2014111272.pre_map.cdb
......\..\2014111272.pre_map.hdb
......\..\2014111272.rtlv.hdb
......\..\2014111272.rtlv_sg.cdb
......\..\2014111272.rtlv_sg_swap.cdb
......\..\2014111272.sgdiff.cdb
......\..\2014111272.sgdiff.hdb
......\..\2014111272.sim.cvwf
......\..\2014111272.sim_ori.vwf
......\..\2014111272.sld_design_entry.sci
......\..\2014111272.sld_design_entry_dsc.sci
......\..\2014111272.syn_hier_info
......\..\2014111272.tan.qmsg
......\..\2014111272.tis_db_list.ddb
......\..\2014111272.tmw_info
......\..\2014111272_global_asgn_op.abo
......\..\mux_joc.tdf
......\..\prev_cmp_2014111272.asm.qmsg
......\..\prev_cmp_2014111272.fit.qmsg
......\..\prev_cmp_2014111272.map.qmsg
......\..\prev_cmp_2014111272.qmsg
......\..\prev_cmp_2014111272.sim.qmsg
......\..\prev_cmp_2014111272.tan.qmsg
......\..\wed.wsf
......\divider1000.bsf
......\divider500.bsf
......\divider500.v
......\divider500.v.bak
......\division.vwf