文件名称:simulation
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2017-10-12
- 文件大小：
- 27kb
- 下载次数：
- 0次
- 提 供 者：
- happyw*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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7segment testbench and velilog相关搜索： 7segment
(系统自动生成,下载前可以参看下载内容)
下载文件列表
7seg.cr.mti
7seg.mpf
seg.v
seg.v.bak
seg_tb.v
seg_tb.v.bak
transcript
vsim.wlf
work
work\@b@c@d_to_7segment
work\@b@c@d_to_7segment\_primary.dat
work\@b@c@d_to_7segment\_primary.dbs
work\@b@c@d_to_7segment\_primary.vhd
work\@b@c@d_to_7segment\verilog.prw
work\@b@c@d_to_7segment\verilog.psm
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.dat
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.dbs
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.vhd
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\verilog.prw
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\verilog.psm
work\_info
work\_temp
work\_temp\vlogz9kxib
work\_vmake
work\binary_to_@b@c@d
work\binary_to_@b@c@d\_primary.dat
work\binary_to_@b@c@d\_primary.dbs
work\binary_to_@b@c@d\_primary.vhd
work\binary_to_@b@c@d\verilog.prw
work\binary_to_@b@c@d\verilog.psm
work\linedecoder
work\linedecoder\_primary.dat
work\linedecoder\_primary.dbs
work\linedecoder\_primary.vhd
work\linedecoder\verilog.prw
work\linedecoder\verilog.psm
7seg.mpf
seg.v
seg.v.bak
seg_tb.v
seg_tb.v.bak
transcript
vsim.wlf
work
work\@b@c@d_to_7segment
work\@b@c@d_to_7segment\_primary.dat
work\@b@c@d_to_7segment\_primary.dbs
work\@b@c@d_to_7segment\_primary.vhd
work\@b@c@d_to_7segment\verilog.prw
work\@b@c@d_to_7segment\verilog.psm
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.dat
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.dbs
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\_primary.vhd
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\verilog.prw
work\@h@b_@s@e@g_@d@e@c@o@d@e@r_@t@b\verilog.psm
work\_info
work\_temp
work\_temp\vlogz9kxib
work\_vmake
work\binary_to_@b@c@d
work\binary_to_@b@c@d\_primary.dat
work\binary_to_@b@c@d\_primary.dbs
work\binary_to_@b@c@d\_primary.vhd
work\binary_to_@b@c@d\verilog.prw
work\binary_to_@b@c@d\verilog.psm
work\linedecoder
work\linedecoder\_primary.dat
work\linedecoder\_primary.dbs
work\linedecoder\_primary.vhd
work\linedecoder\verilog.prw
work\linedecoder\verilog.psm