文件名称:10vhdlexamples
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10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。-10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on.相关搜索： vhdl
加法器
全加器
VHDL
Full
code
in
VHDL
for
LDPC
Selector
in
VHDL
vhdl
full
adder
加法器
全加器
VHDL
Full
code
in
VHDL
for
LDPC
Selector
in
VHDL
vhdl
full
adder
(系统自动生成,下载前可以参看下载内容)
下载文件列表
10_function
...........\10_bit_to_int.vhd
...........\README.TXT
1_ADDER
.......\1_ADDER
.......\.......\1_ADDER.exp
.......\.......\files
.......\.......\.....\L1.rpt
.......\.......\.....\L2.rpt
.......\.......\.....\L3.rpt
.......\.......\workdirs
.......\.......\........\aa
.......\.......\........\..\ADDER.sim
.......\.......\........\..\ADDER.syn
.......\.......\........\..\Anal.info
.......\.......\........\..\Anal.out
.......\.......\........\WORK
.......\.......\........\....\Anal.info
.......\.......\........\....\Anal.out
.......\.......\........\....\BIT_RTL_ADDER.sim
.......\.......\........\....\BIT_RTL_ADDER.syn
.......\1_adder.acf
.......\1_adder.hif
.......\1_adder.mmf
.......\1_ADDER.VHD
.......\bir_rtl_adder.acf
.......\bir_rtl_adder.hif
.......\bir_rtl_adder.mmf
.......\bir_rtl_adder.tdf
.......\bit_rtl_adder.acf
.......\bit_rtl_adder.hif
.......\bit_rtl_adder.mmf
.......\bit_rtl_adder.vhd
.......\LIB.DLS
.......\README.TXT
.......\transcript
.......\U2268397.DLS
.......\work
.......\....\_info
2_ADDER
.......\2_ADDER.VHD
.......\README.TXT
3_MUL
.....\3_MUL.VHD
.....\README.TXT
4_COMP
......\4_COMP.VHD
......\README.TXT
5_MUX2
......\5_MUX2.VHD
......\README.TXT
6_REG
.....\6_REG.VHD
.....\README.TXT
7_shiftreg
..........\7_MVL7_functions.vhd
..........\7_shiftreg.vhd
..........\7_synthesis_types.vhd
..........\7_test_vector.vhd
..........\7_TYPES.VHD
..........\README.TXT
8_BITPKG
........\8_BITPKG.VHD
........\8_bit_rtl_lib.vhd
........\README.TXT
9_MVL7_TYPES
............\9_MVL7_types.vhd
............\README.TXT
...........\10_bit_to_int.vhd
...........\README.TXT
1_ADDER
.......\1_ADDER
.......\.......\1_ADDER.exp
.......\.......\files
.......\.......\.....\L1.rpt
.......\.......\.....\L2.rpt
.......\.......\.....\L3.rpt
.......\.......\workdirs
.......\.......\........\aa
.......\.......\........\..\ADDER.sim
.......\.......\........\..\ADDER.syn
.......\.......\........\..\Anal.info
.......\.......\........\..\Anal.out
.......\.......\........\WORK
.......\.......\........\....\Anal.info
.......\.......\........\....\Anal.out
.......\.......\........\....\BIT_RTL_ADDER.sim
.......\.......\........\....\BIT_RTL_ADDER.syn
.......\1_adder.acf
.......\1_adder.hif
.......\1_adder.mmf
.......\1_ADDER.VHD
.......\bir_rtl_adder.acf
.......\bir_rtl_adder.hif
.......\bir_rtl_adder.mmf
.......\bir_rtl_adder.tdf
.......\bit_rtl_adder.acf
.......\bit_rtl_adder.hif
.......\bit_rtl_adder.mmf
.......\bit_rtl_adder.vhd
.......\LIB.DLS
.......\README.TXT
.......\transcript
.......\U2268397.DLS
.......\work
.......\....\_info
2_ADDER
.......\2_ADDER.VHD
.......\README.TXT
3_MUL
.....\3_MUL.VHD
.....\README.TXT
4_COMP
......\4_COMP.VHD
......\README.TXT
5_MUX2
......\5_MUX2.VHD
......\README.TXT
6_REG
.....\6_REG.VHD
.....\README.TXT
7_shiftreg
..........\7_MVL7_functions.vhd
..........\7_shiftreg.vhd
..........\7_synthesis_types.vhd
..........\7_test_vector.vhd
..........\7_TYPES.VHD
..........\README.TXT
8_BITPKG
........\8_BITPKG.VHD
........\8_bit_rtl_lib.vhd
........\README.TXT
9_MVL7_TYPES
............\9_MVL7_types.vhd
............\README.TXT