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[其它资源] seven_seg
说明:一个verilog代码,该代码很适合初学者熟悉FPGA的开发流程,主要功能为实现七段代码管的显示,主要针对xilinx公司spartan3系列的FPGA-a verilog code that are very suitable for beginners FPGA familiar with the development process, main function of the realization of the code in paragraph 107, xilinx against<虫虫> 在 2008-10-13 上传 | 大小:2.43kb | 下载:0
[其它资源] qiangdaqi111
说明:4路抢答器,vhdl语言编写,绝对真实-four road Responder, vhdl language, absolutely true.<陆已> 在 2008-10-13 上传 | 大小:1.55kb | 下载:0
[其它资源] 2005912101744707
说明:这是一个matlab程序设计方面的文件。有助于学习和应用这一工具。-This is a Matlab program design documents. Contribute to the study and application of this tool.<yangjiqing> 在 2008-10-13 上传 | 大小:69.59kb | 下载:0
[其它资源] MenuScibble
说明:Use an applet calculator procedure of the Java realization, have to have+, -, *, /function. -Use an applet calculator procedure of the J ava realization, have to have, -, *, / function.<王国> 在 2008-10-13 上传 | 大小:1.12kb | 下载:0
[其它资源] Counterd
说明: Return to a container object, can pass this object //Carry on management to the container, such as add to control a piece, with layout operation etc. -Return to a container object, can pass this object / / Carry on management to th e contain<王国> 在 2008-10-13 上传 | 大小:1.6kb | 下载:0
[其它资源] ManagerAdd
说明:Constitution lord the headline of the window way Record the managing person of the debarkationManaging person s number of your importation already existence, please afresh importation-Constitution lord the headline of the wind ow way Record of the<王国> 在 2008-10-13 上传 | 大小:1.28kb | 下载:0