文件名称:decoder
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用verilog编写的bch译码器,包括测试文件,随机加载了比特流,进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
相关搜索: bch
verilog
decoder
BCH
bch
veril
decoder
verilog
verilog
bch
decoder
Verilog
DECODER
bch
verilog
csdn
相关搜索: bch
verilog
decoder
BCH
bch
veril
decoder
verilog
verilog
bch
decoder
Verilog
DECODER
bch
verilog
csdn
(系统自动生成,下载前可以参看下载内容)
下载文件列表
decoder15.udo
decoder15.v
decoder15_summary.html
decoder15_test.v
decoder15_test_v.fdo
decoder15_test_v.udo
oytt.ise
oytt.ise_ISE_Backup
oytt.restore
transcript
vsim.wlf
work
....\decoder15
....\.........\_primary.dat
....\.........\_primary.vhd
....\decoder15_test_v
....\................\_primary.dat
....\................\_primary.vhd
....\glbl
....\....\_primary.dat
....\....\_primary.vhd
....\_info
....\_opt
....\....\D__Xilinx92i_verilog_mti_se_unisims_ver__info
....\....\D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
....\....\work_decoder15_fast.asm
....\....\work_decoder15_fast.dt2
....\....\work_decoder15_test_v_fast.asm
....\....\work_decoder15_test_v_fast.dt2
....\....\work_glbl_fast.asm
....\....\work_glbl_fast.dt2
....\....\work__info
....\....\_deps
....\_opt1
....\.....\D__Xilinx92i_verilog_mti_se_unisims_ver__info
....\.....\D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
....\.....\work_decoder15_fast.asm
....\.....\work_decoder15_fast.dt2
....\.....\work_decoder15_test_v_fast.asm
....\.....\work_decoder15_test_v_fast.dt2
....\.....\work__info
....\.....\_deps
....\_opt2
....\.....\work_decoder15_fast.asm
....\.....\work_decoder15_fast.dt2
....\.....\work_glbl_fast.asm
....\.....\work_glbl_fast.dt2
....\.....\work__info
....\.....\_deps
....\_temp
_xmsgs
decoder15.v
decoder15_summary.html
decoder15_test.v
decoder15_test_v.fdo
decoder15_test_v.udo
oytt.ise
oytt.ise_ISE_Backup
oytt.restore
transcript
vsim.wlf
work
....\decoder15
....\.........\_primary.dat
....\.........\_primary.vhd
....\decoder15_test_v
....\................\_primary.dat
....\................\_primary.vhd
....\glbl
....\....\_primary.dat
....\....\_primary.vhd
....\_info
....\_opt
....\....\D__Xilinx92i_verilog_mti_se_unisims_ver__info
....\....\D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
....\....\work_decoder15_fast.asm
....\....\work_decoder15_fast.dt2
....\....\work_decoder15_test_v_fast.asm
....\....\work_decoder15_test_v_fast.dt2
....\....\work_glbl_fast.asm
....\....\work_glbl_fast.dt2
....\....\work__info
....\....\_deps
....\_opt1
....\.....\D__Xilinx92i_verilog_mti_se_unisims_ver__info
....\.....\D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
....\.....\work_decoder15_fast.asm
....\.....\work_decoder15_fast.dt2
....\.....\work_decoder15_test_v_fast.asm
....\.....\work_decoder15_test_v_fast.dt2
....\.....\work__info
....\.....\_deps
....\_opt2
....\.....\work_decoder15_fast.asm
....\.....\work_decoder15_fast.dt2
....\.....\work_glbl_fast.asm
....\.....\work_glbl_fast.dt2
....\.....\work__info
....\.....\_deps
....\_temp
_xmsgs