文件名称:fpga
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fpga功能实现有限字长响应FIR
用verilog编写
用verilog编写
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下载文件列表
压缩包 : 79419111fpga.rar 列表 fpga\CSA4.v fpga\CSA4.v.bak fpga\booth.v fpga\booth.v.bak fpga\fir.mpf fpga\fir.cr.mti fpga\booth_tp.v fpga\booth_tp.v.bak fpga\vsim.wlf fpga\enter_x.v fpga\enter_x.v.bak fpga\mux_x.v fpga\add_8b.v fpga\full_add1.v fpga\full_add1.v.bak fpga\add_8b.v.bak fpga\CSA4_tp.v fpga\mux_x.v.bak fpga\booth_code.v fpga\add_12b.v fpga\booth_code.v.bak fpga\wallce_tree.v fpga\ying.cr.mti fpga\half_add1.v fpga\half_add1.v.bak fpga\wallce_tree.v.bak fpga\add_12b.v.bak fpga\add_16b.v fpga\add_16b.v.bak fpga\ying.mpf fpga\mux_x_tp.v.bak fpga\wallace_tree_tp.v fpga\half_add1_tp.v fpga\full_add1_tp.v fpga\half_add1_tp.v.bak fpga\full_add1_tp.v.bak fpga\booth_code_tp.v fpga\booth_code_tp.v.bak fpga\CSA4_tp.v.bak fpga\add_8b_tp.v fpga\add_8b_tp.v.bak fpga\enter_x_tp.v fpga\enter_x_tp.v.bak fpga\mux_x_tp.v fpga\add_12b_tp.v fpga\add_12b_tp.v.bak fpga\wallace_tree_tp.v.bak fpga\control.v fpga\add_20b.v fpga\add_20b.v.bak fpga\top.v fpga\wallce_tree_tp.v fpga\wallce_tree_tp.v.bak fpga\add_20b_tp.v fpga\add_20b_tp.v.bak fpga\top.v.bak fpga\control.v.bak fpga\control_tp.v fpga\control_tp.v.bak fpga\Dff.v fpga\Dff.v.bak fpga\Dff_tp.v fpga\Dff_tp.v.bak fpga\mux_h.v fpga\mux_h.v.bak fpga\mux_h_tp.v fpga\mux_h_tp.v.bak fpga\top_tp.v fpga\top_tp.v.bak fpga\vish_stacktrace.vstf fpga\work\_info fpga\work\@dff\verilog.asm fpga\work\@dff\_primary.dat fpga\work\@dff\_primary.vhd fpga\work\@dff_tp\verilog.asm fpga\work\@dff_tp\_primary.dat fpga\work\@dff_tp\_primary.vhd fpga\work\control\verilog.asm fpga\work\control\_primary.dat fpga\work\control\_primary.vhd fpga\work\control_tp\verilog.asm fpga\work\control_tp\_primary.dat fpga\work\control_tp\_primary.vhd fpga\work\mux_h\verilog.asm fpga\work\mux_h\_primary.dat fpga\work\mux_h\_primary.vhd fpga\work\mux_h_tp\verilog.asm fpga\work\mux_h_tp\_primary.dat fpga\work\mux_h_tp\_primary.vhd fpga\work\top\verilog.asm fpga\work\top\_primary.dat fpga\work\top\_primary.vhd fpga\work\top_tp\verilog.asm fpga\work\top_tp\_primary.dat fpga\work\top_tp\_primary.vhd fpga\work\wallce_tree_tp\_primary.vhd fpga\work\wallce_tree_tp\verilog.asm fpga\work\wallce_tree_tp\_primary.dat fpga\work\add_20b\_primary.vhd fpga\work\add_20b\verilog.asm fpga\work\add_20b\_primary.dat fpga\work\add_20b_tp\_primary.vhd fpga\work\add_20b_tp\verilog.asm fpga\work\add_20b_tp\_primary.dat fpga\work\add_12b_tp\verilog.asm fpga\work\add_12b_tp\_primary.dat fpga\work\add_12b_tp\_primary.vhd fpga\work\half_add1_tp\_primary.vhd fpga\work\half_add1_tp\verilog.asm fpga\work\half_add1_tp\_primary.dat fpga\work\full_add1_tp\_primary.vhd fpga\work\full_add1_tp\verilog.asm fpga\work\full_add1_tp\_primary.dat fpga\work\booth_code_tp\_primary.vhd fpga\work\booth_code_tp\verilog.asm fpga\work\booth_code_tp\_primary.dat fpga\work\@c@s@a4_tp\_primary.vhd fpga\work\@c@s@a4_tp\verilog.asm fpga\work\@c@s@a4_tp\_primary.dat fpga\work\add_8b_tp\_primary.vhd fpga\work\add_8b_tp\verilog.asm fpga\work\add_8b_tp\_primary.dat fpga\work\enter_x_tp\_primary.vhd fpga\work\enter_x_tp\verilog.asm fpga\work\enter_x_tp\_primary.dat fpga\work\mux_x_tp\_primary.vhd fpga\work\mux_x_tp\verilog.asm fpga\work\mux_x_tp\_primary.dat fpga\work\mux_x\_primary.vhd fpga\work\mux_x\verilog.asm fpga\work\mux_x\_primary.dat fpga\work\booth_code\_primary.vhd fpga\work\booth_code\verilog.asm fpga\work\booth_code\_primary.dat fpga\work\half_add1\_primary.vhd fpga\work\half_add1\verilog.asm fpga\work\half_add1\_primary.dat fpga\work\add_12b\_primary.vhd fpga\work\add_12b\verilog.asm fpga\work\add_12b\_primary.dat fpga\work\wallce_tree\_primary.vhd fpga\work\wallce_tree\verilog.asm fpga\work\wallce_tree\_primary.dat fpga\work\enter_x\_primary.vhd fpga\work\enter_x\verilog.asm fpga\work\enter_x\_primary.dat fpga\work\@c@s@a4\_primary.vhd fpga\work\@c@s@a4\verilog.asm fpga\work\@c@s@a4\_primary.dat fpga\work\full_add1\_primary.vhd fpga\work\full_add1\verilog.asm fpga\work\full_add1\_primary.dat fpga\work\add_8b\_primary.vhd fpga\work\add_8b\verilog.asm fpga\work\add_8b\_primary.dat fpga\work\booth_tp\verilog.asm fpga\work\booth_tp\_primary.dat fpga\work\booth_tp\_primary.vhd fpga\work\booth\_primary.vhd fpga\work\booth\verilog.asm fpga\work\booth\_primary.dat fpga\transcript fpga\work\@dff fpga\work\@dff_tp fpga\work\control fpga\work\control_tp fpga\work\mux_h fpga\work\mux_h_tp fpga\work\top fpga\work\top_tp fpga\work\wallce_tree_tp fpga\work\add_20b fpga\work\add_20b_tp fpga\work\add_12b_tp fpga\work\half_add1_tp fpga\work\full_add1_tp fpga\work\booth_code_tp fpga\work\@c@s@a4_tp fpga\work\add_8b_tp fpga\work\enter_x_tp fpga\work\mux_x_tp fpga\work\mux_x fpga\work\booth_code fpga\work\half_add1 fpga\work\add_12b fpga\work\wallce_tree fpga\work\enter_x fpga\work\@c@s@a4 fpga\work\full_add1 fpga\work\add_8b fpga\work\booth_tp fpga\work\booth fpga\work fpga