文件名称:sd_IP
介绍说明－－下载内容均来自于网络，请自行研究使用
SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 57578844sd_ip.rar 列表 sd卡读写IP\sd\class.ptf sd卡读写IP\sd\crc_unit_16.v sd卡读写IP\sd\crc_unit_7.v sd卡读写IP\sd\inc\altera_avalon_camelot_sd_controller_regs.h sd卡读写IP\sd\inc sd卡读写IP\sd\mk_user_logic_Camelot_SD_Controller.pl sd卡读写IP\sd\readme.txt sd卡读写IP\sd\sd.v sd卡读写IP\sd\sd_controller.v sd卡读写IP\sd\sd_host.v sd卡读写IP\sd\soft example for nios2\main.cpp sd卡读写IP\sd\soft example for nios2 sd卡读写IP\sd sd卡读写IP