文件名称:OC8051
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USB1.1接口控制器参考设计
文档齐全,,但已经过调试
文档齐全,,但已经过调试
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下载文件列表
压缩包 : 79419137oc8051.rar 列表 OC8051\.nclaunch.dd OC8051\asm\cast.c OC8051\asm\counter_test.asm OC8051\asm\DIV16U.asm OC8051\asm\divmul.c OC8051\asm\fib.c OC8051\asm\gcd.c OC8051\asm\int2bin.c OC8051\asm\interrupt_test.asm OC8051\asm\lcall.asm OC8051\asm\negcnt.c OC8051\asm\r_bank.asm OC8051\asm\serial_test.asm OC8051\asm\sort.c OC8051\asm\sqroot.c OC8051\asm\test.asm OC8051\asm\testall.asm OC8051\asm\testall.c OC8051\asm\timer2_test.asm OC8051\asm\timer_test.asm OC8051\asm\xram.c OC8051\asm\xram_m.c OC8051\asm\xrom_test.asm OC8051\asm\CVS\Entries OC8051\asm\CVS\Repository OC8051\asm\CVS\Root OC8051\asm\CVS OC8051\asm\hex\cast.hex OC8051\asm\hex\counter_test.hex OC8051\asm\hex\div16u.hex OC8051\asm\hex\divmul.hex OC8051\asm\hex\fib.hex OC8051\asm\hex\gcd.hex OC8051\asm\hex\int2bin.hex OC8051\asm\hex\interrupt_test.hex OC8051\asm\hex\lcall.hex OC8051\asm\hex\negcnt.hex OC8051\asm\hex\r_bank.hex OC8051\asm\hex\serial_test.hex OC8051\asm\hex\sort.hex OC8051\asm\hex\sqroot.hex OC8051\asm\hex\testall.hex OC8051\asm\hex\timer_test.hex OC8051\asm\hex\xram.hex OC8051\asm\hex\xram_m.ihx OC8051\asm\hex\CVS\Entries OC8051\asm\hex\CVS\Repository OC8051\asm\hex\CVS\Root OC8051\asm\hex\CVS OC8051\asm\hex OC8051\asm\in\cast.in OC8051\asm\in\counter_test.in OC8051\asm\in\div16u.in OC8051\asm\in\divmul.in OC8051\asm\in\fib.in OC8051\asm\in\gcd.in OC8051\asm\in\int2bin.in OC8051\asm\in\interrupt_test.in OC8051\asm\in\lcall.in OC8051\asm\in\negcnt.in OC8051\asm\in\oc8051_xrom.in OC8051\asm\in\r_bank.in OC8051\asm\in\serial_test.in OC8051\asm\in\sort.in OC8051\asm\in\sqroot.in OC8051\asm\in\testall.in OC8051\asm\in\test_xram.in OC8051\asm\in\timer2_test.in OC8051\asm\in\timer_test.in OC8051\asm\in\xram.in OC8051\asm\in\xram_m.in OC8051\asm\in\xrom_test.in OC8051\asm\in\CVS\Entries OC8051\asm\in\CVS\Repository OC8051\asm\in\CVS\Root OC8051\asm\in\CVS OC8051\asm\in OC8051\asm\v\cast.v OC8051\asm\v\counter_test.v OC8051\asm\v\div16u.v OC8051\asm\v\divmul.v OC8051\asm\v\fib.v OC8051\asm\v\gcd.v OC8051\asm\v\int2bin.v OC8051\asm\v\interrupt_test.v OC8051\asm\v\lcall.v OC8051\asm\v\negcnt.v OC8051\asm\v\r_bank.v OC8051\asm\v\serial_test.v OC8051\asm\v\sort.v OC8051\asm\v\sqroot.v OC8051\asm\v\testall.v OC8051\asm\v\timer_test.v OC8051\asm\v\xram.v OC8051\asm\v\xram_m.v OC8051\asm\v\CVS\Entries OC8051\asm\v\CVS\Repository OC8051\asm\v\CVS\Root OC8051\asm\v\CVS OC8051\asm\v OC8051\asm\vec\cast.vec OC8051\asm\vec\counter_test.vec OC8051\asm\vec\div16u.vec OC8051\asm\vec\divmul.vec OC8051\asm\vec\fib.vec OC8051\asm\vec\gcd.vec OC8051\asm\vec\int2bin.vec OC8051\asm\vec\interrupt_test.vec OC8051\asm\vec\lcall.vec OC8051\asm\vec\negcnt.vec OC8051\asm\vec\r_bank.vec OC8051\asm\vec\serial_test.vec OC8051\asm\vec\sort.vec OC8051\asm\vec\sqroot.vec OC8051\asm\vec\testall.vec OC8051\asm\vec\test_xram.vec OC8051\asm\vec\timer2_test.vec OC8051\asm\vec\timer_test.vec OC8051\asm\vec\xram_m.vec OC8051\asm\vec\xrom_test.vec OC8051\asm\vec\CVS\Entries OC8051\asm\vec\CVS\Repository OC8051\asm\vec\CVS\Root OC8051\asm\vec\CVS OC8051\asm\vec OC8051\asm OC8051\bench\CVS\Entries OC8051\bench\CVS\Repository OC8051\bench\CVS\Root OC8051\bench\CVS OC8051\bench\in\7seg.in OC8051\bench\in\blinkP10.in OC8051\bench\in\BLINKY.in OC8051\bench\in\calculator.in OC8051\bench\in\cast.in OC8051\bench\in\cordic.in OC8051\bench\in\counter_test.in OC8051\bench\in\Crc.in OC8051\bench\in\cubicroots.in OC8051\bench\in\div16u.in OC8051\bench\in\divmul.in OC8051\bench\in\fib.in OC8051\bench\in\gcd.in OC8051\bench\in\int2bin.in OC8051\bench\in\interrupt_test.in OC8051\bench\in\interrupt_test2.in OC8051\bench\in\lcall.in OC8051\bench\in\mx_test.in OC8051\bench\in\mx_test.in~ OC8051\bench\in\negcnt.in OC8051\bench\in\normalize.in OC8051\bench\in\oc8051_rom.in OC8051\bench\in\oc8051_xrom.in OC8051\bench\in\pca_test.in OC8051\bench\in\pwm.in OC8051\bench\in\r_bank.in OC8051\bench\in\serial_test.in OC8051\bench\in\Sieve.in OC8051\bench\in\sort.in OC8051\bench\in\sqroot.in OC8051\bench\in\sqroot_1.in OC8051\bench\in\src.in OC8051\bench\in\testall.in OC8051\bench\in\test_xram.in OC8051\bench\in\timer0.in OC8051\bench\in\timer2_test.in OC8051\bench\in\timer_test.in OC8051\bench\in\wdog1.in OC8051\bench\in\wdog2.in OC8051\bench\in\wdog3.in OC8051\bench\in\xram.in OC8051\bench\in\xram_m.in OC8051\bench\in\xrom_test.in OC8051\bench\in\CVS\Entries OC8051\bench\in\CVS\Repository OC8051\bench\in\CVS\Root OC8051\bench\in\CVS OC8051\bench\in OC8051\bench\vec\CVS\Entries OC8051\bench\vec\CVS\Repository OC8051\bench\vec\CVS\Root OC8051\bench\vec\CVS OC8051\bench\vec OC8051\bench\verilog\oc8051_fpga_tb.v OC8051\bench\verilog\oc8051_serial.v OC8051\bench\verilog\oc8051_tb.v OC8051\bench\verilog\oc8051_timescale.v OC8051\bench\verilog\oc8051_uart_test.v OC8051\bench\verilog\oc8051_xram.v OC8051\bench\verilog\oc8051_xrom.v OC8051\bench\verilog\CVS\Entries OC8051\bench\verilog\CVS\Repository OC8051\bench\verilog\CVS\Root OC8051\bench\verilog\CVS OC8051\bench\verilog OC8051\bench OC8051\CVS\Entries OC8051\CVS\Repository OC8051\CVS\Root OC8051\CVS OC8051\doc\CVS\Entries OC8051\doc\CVS\Repository OC8051\doc\CVS\Root OC8051\doc\CVS OC8051\doc\pdf\oc8051_spec.pdf OC8051\doc\pdf\CVS\Entries OC8051\doc\pdf\CVS\Repository OC8051\doc\pdf\CVS\Root OC8051\doc\pdf\CVS OC8051\doc\pdf OC8051\doc\src\oc8051_design.doc OC8051\doc\src\CVS\Entries OC8051\doc\src\CVS\Repository OC8051\doc\src\CVS\Root OC8051\doc\src\CVS OC8051\doc\src OC8051\doc OC8051\rtl\CVS\Entries OC8051\rtl\CVS\Repository OC8051\rtl\CVS\Root OC8051\rtl\CVS OC8051\rtl\verilog\oc8051_acc.v OC8051\rtl\verilog\oc8051_alu.v OC8051\rtl\verilog\oc8051_alu_src_sel.v OC8051\rtl\verilog\oc8051_alu_test.v OC8051\rtl\verilog\oc8051_b_register.v OC8051\rtl\verilog\oc8051_cache_ram.v OC8051\rtl\verilog\oc8051_comp.v OC8051\rtl\verilog\oc8051_cy_select.v OC8051\rtl\verilog\oc8051_decoder.v OC8051\rtl\verilog\oc8051_defines.v OC8051\rtl\verilog\oc8051_divide.v OC8051\rtl\verilog\oc8051_dptr.v OC8051\rtl\verilog\oc8051_icache.v OC8051\rtl\verilog\oc8051_indi_addr.v OC8051\rtl\verilog\oc8051_int.v OC8051\rtl\verilog\oc8051_memory_interface.v OC8051\rtl\verilog\oc8051_multiply.v OC8051\rtl\verilog\oc8051_ports.v OC8051\rtl\verilog\oc8051_psw.v OC8051\rtl\verilog\oc8051_ram_256x8_two_bist.v OC8051\rtl\verilog\oc8051_ram_64x32_dual_bist.v OC8051\rtl\verilog\oc8051_ram_top.v OC8051\rtl\verilog\oc8051_rom.v OC8051\rtl\verilog\oc8051_sfr.v OC8051\rtl\verilog\oc8051_sp.v OC8051\rtl\verilog\oc8051_tc.v OC8051\rtl\verilog\oc8051_tc2.v OC8051\rtl\verilog\oc8051_timescale.v OC8051\rtl\verilog\oc8051_top.v OC8051\rtl\verilog\oc8051_uart.v OC8051\rtl\verilog\oc8051_wb_iinterface.v OC8051\rtl\verilog\read.me OC8051\rtl\verilog\CVS\Entries OC8051\rtl\verilog\CVS\Repository OC8051\rtl\verilog\CVS\Root OC8051\rtl\verilog\CVS OC8051\rtl\verilog OC8051\rtl OC8051\sim\CVS\Entries OC8051\sim\CVS\Repository OC8051\sim\CVS\Root OC8051\sim\CVS OC8051\sim\rtl_sim\oc8051_ea.in OC8051\sim\rtl_sim\oc8051_eai.in OC8051\sim\rtl_sim\oc8051_eax.in OC8051\sim\rtl_sim\bin\cds.lib OC8051\sim\rtl_sim\bin\hdl.var OC8051\sim\rtl_sim\bin\CVS\Entries OC8051\sim\rtl_sim\bin\CVS\Repository OC8051\sim\rtl_sim\bin\CVS\Root OC8051\sim\rtl_sim\bin\CVS OC8051\sim\rtl_sim\bin\INCA_libs\CVS\Entries OC8051\sim\rtl_sim\bin\INCA_libs\CVS\Repository OC8051\sim\rtl_sim\bin\INCA_libs\CVS\Root OC8051\sim\rtl_sim\bin\INCA_libs\CVS OC8051\sim\rtl_sim\bin\INCA_libs\worklib\inca.linux.138.pak OC8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Entries OC8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Repository OC8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS\Root OC8051\sim\rtl_sim\bin\INCA_libs\worklib\CVS OC8051\sim\rtl_sim\bin\INCA_libs\worklib OC8051\sim\rtl_sim\bin\INCA_libs OC8051\sim\rtl_sim\bin OC8051\sim\rtl_sim\CVS\Entries OC8051\sim\rtl_sim\CVS\Repository OC8051\sim\rtl_sim\CVS\Root OC8051\sim\rtl_sim\CVS OC8051\sim\rtl_sim\log\ncelab.log OC8051\sim\rtl_sim\log\ncsim.log OC8051\sim\rtl_sim\log\ncvlog.log OC8051\sim\rtl_sim\log\CVS\Entries OC8051\sim\rtl_sim\log\CVS\Repository OC8051\sim\rtl_sim\log\CVS\Root OC8051\sim\rtl_sim\log\CVS OC8051\sim\rtl_sim\log OC8051\sim\rtl_sim\out\cast.out OC8051\sim\rtl_sim\out\counter_test.out OC8051\sim\rtl_sim\out\div16u.out OC8051\sim\rtl_sim\out\divmul.out OC8051\sim\rtl_sim\out\fib.out OC8051\sim\rtl_sim\out\gcd.out OC8051\sim\rtl_sim\out\int2bin.out OC8051\sim\rtl_sim\out\interrupt_test.out OC8051\sim\rtl_sim\out\lcall.out OC8051\sim\rtl_sim\out\ncelab.out OC8051\sim\rtl_sim\out\ncprep.out OC8051\sim\rtl_sim\out\ncvlog.out OC8051\sim\rtl_sim\out\negcnt.out OC8051\sim\rtl_sim\out\r_bank.out OC8051\sim\rtl_sim\out\serial_test.out OC8051\sim\rtl_sim\out\sort.out OC8051\sim\rtl_sim\out\sqroot.out OC8051\sim\rtl_sim\out\testall.out OC8051\sim\rtl_sim\out\timer.out OC8051\sim\rtl_sim\out\timer_test.out OC8051\sim\rtl_sim\out\xram_m.out OC8051\sim\rtl_sim\out\xrom_m.out OC8051\sim\rtl_sim\out\CVS\Entries OC8051\sim\rtl_sim\out\CVS\Repository OC8051\sim\rtl_sim\out\CVS\Root OC8051\sim\rtl_sim\out\CVS OC8051\sim\rtl_sim\out\waves.shm\CVS\Entries OC8051\sim\rtl_sim\out\waves.shm\CVS\Repository OC8051\sim\rtl_sim\out\waves.shm\CVS\Root OC8051\sim\rtl_sim\out\waves.shm\CVS OC8051\sim\rtl_sim\out\waves.shm OC8051\sim\rtl_sim\out OC8051\sim\rtl_sim\run\internal.do OC8051\sim\rtl_sim\run\make OC8051\sim\rtl_sim\run\make_fpga OC8051\sim\rtl_sim\run\make_verilog OC8051\sim\rtl_sim\run\oc8051_defines.v OC8051\sim\rtl_sim\run\oc8051_timescale.v OC8051\sim\rtl_sim\run\run OC8051\sim\rtl_sim\run\run_sim.scr OC8051\sim\rtl_sim\run\verilog.log OC8051\sim\rtl_sim\run\CVS\Entries OC8051\sim\rtl_sim\run\CVS\Repository OC8051\sim\rtl_sim\run\CVS\Root OC8051\sim\rtl_sim\run\CVS OC8051\sim\rtl_sim\run OC8051\sim\rtl_sim\src\CVS\Entries OC8051\sim\rtl_sim\src\CVS\Repository OC8051\sim\rtl_sim\src\CVS\Root OC8051\sim\rtl_sim\src\CVS OC8051\sim\rtl_sim\src\verilog\CVS\Entries OC8051\sim\rtl_sim\src\verilog\CVS\Repository OC8051\sim\rtl_sim\src\verilog\CVS\Root OC8051\sim\rtl_sim\src\verilog\CVS OC8051\sim\rtl_sim\src\verilog OC8051\sim\rtl_sim\src OC8051\sim\rtl_sim OC8051\sim OC8051\sw\oc8051_Rom_Maker.exe OC8051\sw\read.me OC8051\sw\CVS\Entries OC8051\sw\CVS\Repository OC8051\sw\CVS\Root OC8051\sw\CVS OC8051\sw\source\p8051Rom.dof OC8051\sw\source\p8051Rom.dpr OC8051\sw\source\p8051Rom.res OC8051\sw\source\uMain.dcu OC8051\sw\source\uMain.dfm OC8051\sw\source\uMain.pas OC8051\sw\source\CVS\Entries OC8051\sw\source\CVS\Repository OC8051\sw\source\CVS\Root OC8051\sw\source\CVS OC8051\sw\source OC8051\sw OC8051\syn\CVS\Entries OC8051\syn\CVS\Repository OC8051\syn\CVS\Root OC8051\syn\CVS OC8051\syn\src\CVS\Entries OC8051\syn\src\CVS\Repository OC8051\syn\src\CVS\Root OC8051\syn\src\CVS OC8051\syn\src\verilog\disp.v OC8051\syn\src\verilog\oc8051_cache_ram.v OC8051\syn\src\verilog\oc8051_fpga_top.v OC8051\syn\src\verilog\oc8051_ram.v OC8051\syn\src\verilog\oc8051_rom.v OC8051\syn\src\verilog\read.me OC8051\syn\src\verilog\CVS\Entries OC8051\syn\src\verilog\CVS\Repository OC8051\syn\src\verilog\CVS\Root OC8051\syn\src\verilog\CVS OC8051\syn\src\verilog OC8051\syn\src OC8051\syn\synplify\oc8051.prd OC8051\syn\synplify\oc8051.prj OC8051\syn\synplify\CVS\Entries OC8051\syn\synplify\CVS\Repository OC8051\syn\synplify\CVS\Root OC8051\syn\synplify\CVS OC8051\syn\synplify\rev_1\CVS\Entries OC8051\syn\synplify\rev_1\CVS\Repository OC8051\syn\synplify\rev_1\CVS\Root OC8051\syn\synplify\rev_1\CVS OC8051\syn\synplify\rev_1 OC8051\syn\synplify\rev_2\CVS\Entries OC8051\syn\synplify\rev_2\CVS\Repository OC8051\syn\synplify\rev_2\CVS\Root OC8051\syn\synplify\rev_2\CVS OC8051\syn\synplify\rev_2 OC8051\syn\synplify\rev_3\CVS\Entries OC8051\syn\synplify\rev_3\CVS\Repository OC8051\syn\synplify\rev_3\CVS\Root OC8051\syn\synplify\rev_3\CVS OC8051\syn\synplify\rev_3 OC8051\syn\synplify OC8051\syn OC8051