文件名称:DCT
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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
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压缩包 : 23825774dct.rar 列表 DCT\db\altsyncram_rnu.tdf DCT\db\dct_syn.(0).cnf.cdb DCT\db\dct_syn.(0).cnf.hdb DCT\db\dct_syn.(1).cnf.cdb DCT\db\dct_syn.(1).cnf.hdb DCT\db\dct_syn.(10).cnf.cdb DCT\db\dct_syn.(10).cnf.hdb DCT\db\dct_syn.(11).cnf.cdb DCT\db\dct_syn.(11).cnf.hdb DCT\db\dct_syn.(12).cnf.cdb DCT\db\dct_syn.(12).cnf.hdb DCT\db\dct_syn.(13).cnf.cdb DCT\db\dct_syn.(13).cnf.hdb DCT\db\dct_syn.(14).cnf.cdb DCT\db\dct_syn.(14).cnf.hdb DCT\db\dct_syn.(15).cnf.cdb DCT\db\dct_syn.(15).cnf.hdb DCT\db\dct_syn.(16).cnf.cdb DCT\db\dct_syn.(16).cnf.hdb DCT\db\dct_syn.(17).cnf.cdb DCT\db\dct_syn.(17).cnf.hdb DCT\db\dct_syn.(18).cnf.cdb DCT\db\dct_syn.(18).cnf.hdb DCT\db\dct_syn.(19).cnf.cdb DCT\db\dct_syn.(19).cnf.hdb DCT\db\dct_syn.(2).cnf.cdb DCT\db\dct_syn.(2).cnf.hdb DCT\db\dct_syn.(20).cnf.cdb DCT\db\dct_syn.(20).cnf.hdb DCT\db\dct_syn.(21).cnf.cdb DCT\db\dct_syn.(21).cnf.hdb DCT\db\dct_syn.(22).cnf.cdb DCT\db\dct_syn.(22).cnf.hdb DCT\db\dct_syn.(23).cnf.cdb DCT\db\dct_syn.(23).cnf.hdb DCT\db\dct_syn.(24).cnf.cdb DCT\db\dct_syn.(24).cnf.hdb DCT\db\dct_syn.(25).cnf.cdb DCT\db\dct_syn.(25).cnf.hdb DCT\db\dct_syn.(26).cnf.cdb DCT\db\dct_syn.(26).cnf.hdb DCT\db\dct_syn.(27).cnf.cdb DCT\db\dct_syn.(27).cnf.hdb DCT\db\dct_syn.(28).cnf.cdb DCT\db\dct_syn.(28).cnf.hdb DCT\db\dct_syn.(29).cnf.cdb DCT\db\dct_syn.(29).cnf.hdb DCT\db\dct_syn.(3).cnf.cdb DCT\db\dct_syn.(3).cnf.hdb DCT\db\dct_syn.(30).cnf.cdb DCT\db\dct_syn.(30).cnf.hdb DCT\db\dct_syn.(31).cnf.cdb DCT\db\dct_syn.(31).cnf.hdb DCT\db\dct_syn.(32).cnf.cdb DCT\db\dct_syn.(32).cnf.hdb DCT\db\dct_syn.(33).cnf.cdb DCT\db\dct_syn.(33).cnf.hdb DCT\db\dct_syn.(34).cnf.cdb DCT\db\dct_syn.(34).cnf.hdb DCT\db\dct_syn.(35).cnf.cdb DCT\db\dct_syn.(35).cnf.hdb DCT\db\dct_syn.(36).cnf.cdb DCT\db\dct_syn.(36).cnf.hdb DCT\db\dct_syn.(37).cnf.cdb DCT\db\dct_syn.(37).cnf.hdb DCT\db\dct_syn.(38).cnf.cdb DCT\db\dct_syn.(38).cnf.hdb DCT\db\dct_syn.(39).cnf.cdb DCT\db\dct_syn.(39).cnf.hdb DCT\db\dct_syn.(4).cnf.cdb DCT\db\dct_syn.(4).cnf.hdb DCT\db\dct_syn.(40).cnf.cdb DCT\db\dct_syn.(40).cnf.hdb DCT\db\dct_syn.(41).cnf.cdb DCT\db\dct_syn.(41).cnf.hdb DCT\db\dct_syn.(42).cnf.cdb DCT\db\dct_syn.(42).cnf.hdb DCT\db\dct_syn.(43).cnf.cdb DCT\db\dct_syn.(43).cnf.hdb DCT\db\dct_syn.(44).cnf.cdb DCT\db\dct_syn.(44).cnf.hdb DCT\db\dct_syn.(45).cnf.cdb DCT\db\dct_syn.(45).cnf.hdb DCT\db\dct_syn.(46).cnf.cdb DCT\db\dct_syn.(46).cnf.hdb DCT\db\dct_syn.(47).cnf.cdb DCT\db\dct_syn.(47).cnf.hdb DCT\db\dct_syn.(48).cnf.cdb DCT\db\dct_syn.(48).cnf.hdb DCT\db\dct_syn.(49).cnf.cdb DCT\db\dct_syn.(49).cnf.hdb DCT\db\dct_syn.(5).cnf.cdb DCT\db\dct_syn.(5).cnf.hdb DCT\db\dct_syn.(50).cnf.cdb DCT\db\dct_syn.(50).cnf.hdb DCT\db\dct_syn.(51).cnf.cdb DCT\db\dct_syn.(51).cnf.hdb DCT\db\dct_syn.(52).cnf.cdb DCT\db\dct_syn.(52).cnf.hdb DCT\db\dct_syn.(53).cnf.cdb DCT\db\dct_syn.(53).cnf.hdb DCT\db\dct_syn.(54).cnf.cdb DCT\db\dct_syn.(54).cnf.hdb DCT\db\dct_syn.(55).cnf.cdb DCT\db\dct_syn.(55).cnf.hdb DCT\db\dct_syn.(56).cnf.cdb DCT\db\dct_syn.(56).cnf.hdb DCT\db\dct_syn.(57).cnf.cdb DCT\db\dct_syn.(57).cnf.hdb DCT\db\dct_syn.(58).cnf.cdb DCT\db\dct_syn.(58).cnf.hdb DCT\db\dct_syn.(59).cnf.cdb DCT\db\dct_syn.(59).cnf.hdb DCT\db\dct_syn.(6).cnf.cdb DCT\db\dct_syn.(6).cnf.hdb DCT\db\dct_syn.(60).cnf.cdb DCT\db\dct_syn.(60).cnf.hdb DCT\db\dct_syn.(61).cnf.cdb DCT\db\dct_syn.(61).cnf.hdb DCT\db\dct_syn.(62).cnf.cdb DCT\db\dct_syn.(62).cnf.hdb DCT\db\dct_syn.(63).cnf.cdb DCT\db\dct_syn.(63).cnf.hdb DCT\db\dct_syn.(64).cnf.cdb DCT\db\dct_syn.(64).cnf.hdb DCT\db\dct_syn.(65).cnf.cdb DCT\db\dct_syn.(65).cnf.hdb DCT\db\dct_syn.(66).cnf.cdb DCT\db\dct_syn.(66).cnf.hdb DCT\db\dct_syn.(67).cnf.cdb DCT\db\dct_syn.(67).cnf.hdb DCT\db\dct_syn.(68).cnf.cdb DCT\db\dct_syn.(68).cnf.hdb DCT\db\dct_syn.(69).cnf.cdb DCT\db\dct_syn.(69).cnf.hdb DCT\db\dct_syn.(7).cnf.cdb DCT\db\dct_syn.(7).cnf.hdb DCT\db\dct_syn.(70).cnf.cdb DCT\db\dct_syn.(70).cnf.hdb DCT\db\dct_syn.(71).cnf.cdb DCT\db\dct_syn.(71).cnf.hdb DCT\db\dct_syn.(72).cnf.cdb DCT\db\dct_syn.(72).cnf.hdb DCT\db\dct_syn.(73).cnf.cdb DCT\db\dct_syn.(73).cnf.hdb DCT\db\dct_syn.(74).cnf.cdb DCT\db\dct_syn.(74).cnf.hdb DCT\db\dct_syn.(75).cnf.cdb DCT\db\dct_syn.(75).cnf.hdb DCT\db\dct_syn.(76).cnf.cdb DCT\db\dct_syn.(76).cnf.hdb DCT\db\dct_syn.(77).cnf.cdb DCT\db\dct_syn.(77).cnf.hdb DCT\db\dct_syn.(78).cnf.cdb DCT\db\dct_syn.(78).cnf.hdb DCT\db\dct_syn.(79).cnf.cdb DCT\db\dct_syn.(79).cnf.hdb DCT\db\dct_syn.(8).cnf.cdb DCT\db\dct_syn.(8).cnf.hdb DCT\db\dct_syn.(80).cnf.cdb DCT\db\dct_syn.(80).cnf.hdb DCT\db\dct_syn.(81).cnf.cdb DCT\db\dct_syn.(81).cnf.hdb DCT\db\dct_syn.(82).cnf.cdb DCT\db\dct_syn.(82).cnf.hdb DCT\db\dct_syn.(83).cnf.cdb DCT\db\dct_syn.(83).cnf.hdb DCT\db\dct_syn.(84).cnf.cdb DCT\db\dct_syn.(84).cnf.hdb DCT\db\dct_syn.(85).cnf.cdb DCT\db\dct_syn.(85).cnf.hdb DCT\db\dct_syn.(86).cnf.cdb DCT\db\dct_syn.(86).cnf.hdb DCT\db\dct_syn.(87).cnf.cdb DCT\db\dct_syn.(87).cnf.hdb DCT\db\dct_syn.(88).cnf.cdb DCT\db\dct_syn.(88).cnf.hdb DCT\db\dct_syn.(9).cnf.cdb DCT\db\dct_syn.(9).cnf.hdb DCT\db\dct_syn.asm.qmsg DCT\db\dct_syn.asm_labs.ddb DCT\db\dct_syn.atom.rvd DCT\db\dct_syn.cbx.xml DCT\db\dct_syn.cmp.cdb DCT\db\dct_syn.cmp.hdb DCT\db\dct_syn.cmp.kpt DCT\db\dct_syn.cmp.logdb DCT\db\dct_syn.cmp.rdb DCT\db\dct_syn.cmp.tdb DCT\db\dct_syn.cmp0.ddb DCT\db\dct_syn.cmp2.ddb DCT\db\dct_syn.dbp DCT\db\dct_syn.db_info DCT\db\dct_syn.eco.cdb DCT\db\dct_syn.eda.qmsg DCT\db\dct_syn.eds_overflow DCT\db\dct_syn.fit.qmsg DCT\db\dct_syn.fnsim.hdb DCT\db\dct_syn.fnsim.qmsg DCT\db\dct_syn.hier_info DCT\db\dct_syn.hif DCT\db\dct_syn.map.cdb DCT\db\dct_syn.map.hdb DCT\db\dct_syn.map.logdb DCT\db\dct_syn.map.qmsg DCT\db\dct_syn.pre_map.cdb DCT\db\dct_syn.pre_map.hdb DCT\db\dct_syn.psp DCT\db\dct_syn.rpp.qmsg DCT\db\dct_syn.rtlv.hdb DCT\db\dct_syn.rtlv_sg.cdb DCT\db\dct_syn.rtlv_sg_swap.cdb DCT\db\dct_syn.sgate.rvd DCT\db\dct_syn.sgate_sm.rvd DCT\db\dct_syn.sgdiff.cdb DCT\db\dct_syn.sgdiff.hdb DCT\db\dct_syn.signalprobe.cdb DCT\db\dct_syn.sim.hdb DCT\db\dct_syn.sim.qmsg DCT\db\dct_syn.sim.rdb DCT\db\dct_syn.sim.vwf DCT\db\dct_syn.sld_design_entry.sci DCT\db\dct_syn.sld_design_entry_dsc.sci DCT\db\dct_syn.syn_hier_info DCT\db\dct_syn.tan.qmsg DCT\db\dct_syn0.rtl.mif DCT\db\mac_out_ra42.tdf DCT\db\mult_1g71.tdf DCT\db\mult_1v01.tdf DCT\db\mult_4q01.tdf DCT\db\mult_gm01.tdf DCT\db\mux_42d.tdf DCT\db\mux_qlc.tdf DCT\db\rom0_dctu_70beb102.hdl.mif DCT\db\rom0_dctu_70beb2e3.hdl.mif DCT\db\rom0_dctu_70beb53a.hdl.mif DCT\db\rom0_dctu_70beb6db.hdl.mif DCT\db\rom0_dctu_70bf3130.hdl.mif DCT\db\rom0_dctu_70bf32d1.hdl.mif DCT\db\rom0_dctu_70bf3508.hdl.mif DCT\db\rom0_dctu_70bf36e9.hdl.mif DCT\db\rom0_dctu_940c0811.hdl.mif DCT\db\rom0_dctu_940c09f5.hdl.mif DCT\db\rom0_dctu_940c7d7d.hdl.mif DCT\db\rom0_dctu_940c7d9c.hdl.mif DCT\db\rom0_dctu_940c8558.hdl.mif DCT\db\rom0_dctu_940c8579.hdl.mif DCT\db\rom0_dctu_940caba0.hdl.mif DCT\db\rom0_dctu_940cabc0.hdl.mif DCT\db\rom0_dctu_aacad44c.hdl.mif DCT\db\rom0_dctu_aacad5af.hdl.mif DCT\db\rom0_dctu_aacfa207.hdl.mif DCT\db\rom0_dctu_aacfa266.hdl.mif DCT\db\rom0_dctu_aad08815.hdl.mif DCT\db\rom0_dctu_aad0886d.hdl.mif DCT\db\rom0_dctu_aad0940c.hdl.mif DCT\db\rom0_dctu_aad09464.hdl.mif DCT\db\rom0_dctu_adc48cd7.hdl.mif DCT\db\rom0_dctu_adc4906e.hdl.mif DCT\db\rom0_dctu_adc490f0.hdl.mif DCT\db\rom0_dctu_adc49ca9.hdl.mif DCT\db\rom0_dctu_add86c05.hdl.mif DCT\db\rom0_dctu_add86ca6.hdl.mif DCT\db\rom0_dctu_addb7c4e.hdl.mif DCT\db\rom0_dctu_addb7c6f.hdl.mif DCT\db\rom0_dctu_b3440689.hdl.mif DCT\db\rom0_dctu_b34406ea.hdl.mif DCT\db\rom0_dctu_b3440a90.hdl.mif DCT\db\rom0_dctu_b3440af3.hdl.mif DCT\db\rom0_dctu_b3468558.hdl.mif DCT\db\rom0_dctu_b3468579.hdl.mif DCT\db\rom0_dctu_b3469142.hdl.mif DCT\db\rom0_dctu_b34691a3.hdl.mif DCT\db\rom0_dctu_bd6db67.hdl.mif DCT\db\rom0_dctu_bd6db99.hdl.mif DCT\db\rom0_dctu_bd6df2e.hdl.mif DCT\db\rom0_dctu_bd6dfd0.hdl.mif DCT\db\rom0_dctu_bd74379.hdl.mif DCT\db\rom0_dctu_bd74397.hdl.mif DCT\db\rom0_dctu_bd74760.hdl.mif DCT\db\rom0_dctu_bd7478e.hdl.mif DCT\db\rom0_dctu_e74c29b.hdl.mif DCT\db\rom0_dctu_e74c2fa.hdl.mif DCT\db\rom0_dctu_e74efd1.hdl.mif DCT\db\rom0_dctu_e74eff0.hdl.mif DCT\db\rom0_dctu_e776d31.hdl.mif DCT\db\rom0_dctu_e776d92.hdl.mif DCT\db\rom0_dctu_e77709b.hdl.mif DCT\db\rom0_dctu_e7770b8.hdl.mif DCT\db\rom0_dctu_ff42d2bd.hdl.mif DCT\db\rom0_dctu_ff42d2de.hdl.mif DCT\db\rom0_dctu_ff42d684.hdl.mif DCT\db\rom0_dctu_ff42d6a7.hdl.mif DCT\db\rom0_dctu_ff4f5085.hdl.mif DCT\db\rom0_dctu_ff4f50e6.hdl.mif DCT\db\rom0_dctu_ff4f6c3f.hdl.mif DCT\db\rom0_dctu_ff4f6c5c.hdl.mif DCT\db\wed.zsf DCT\db DCT\dct.bsf DCT\dct.v DCT\dctsim2\bench_top.v DCT\dctsim2\cycloneii_atoms.v DCT\dctsim2\dct.v DCT\dctsim2\dctsim.cr.mti DCT\dctsim2\dctsim.mpf DCT\dctsim2\dctu.v DCT\dctsim2\dctub.v DCT\dctsim2\dct_2d.m DCT\dctsim2\dct_cos_table.v DCT\dctsim2\dct_mac.v DCT\dctsim2\dct_syn.v DCT\dctsim2\dct仿真波形及分析.doc DCT\dctsim2\fdct.v DCT\dctsim2\transcript DCT\dctsim2\vsim.wlf DCT\dctsim2\wave.do DCT\dctsim2\work\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e\verilog.asm DCT\dctsim2\work\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e\_primary.dat DCT\dctsim2\work\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e\_primary.vhd DCT\dctsim2\work\@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e DCT\dctsim2\work\bench_top\verilog.asm DCT\dctsim2\work\bench_top\_primary.dat DCT\dctsim2\work\bench_top\_primary.vhd DCT\dctsim2\work\bench_top DCT\dctsim2\work\cycloneii_and1\verilog.asm DCT\dctsim2\work\cycloneii_and1\_primary.dat DCT\dctsim2\work\cycloneii_and1\_primary.vhd DCT\dctsim2\work\cycloneii_and1 DCT\dctsim2\work\cycloneii_and16\verilog.asm DCT\dctsim2\work\cycloneii_and16\_primary.dat DCT\dctsim2\work\cycloneii_and16\_primary.vhd DCT\dctsim2\work\cycloneii_and16 DCT\dctsim2\work\cycloneii_asmiblock\verilog.asm DCT\dctsim2\work\cycloneii_asmiblock\_primary.dat DCT\dctsim2\work\cycloneii_asmiblock\_primary.vhd DCT\dctsim2\work\cycloneii_asmiblock DCT\dctsim2\work\cycloneii_asynch_io\verilog.asm DCT\dctsim2\work\cycloneii_asynch_io\_primary.dat DCT\dctsim2\work\cycloneii_asynch_io\_primary.vhd DCT\dctsim2\work\cycloneii_asynch_io DCT\dctsim2\work\cycloneii_b17mux21\verilog.asm DCT\dctsim2\work\cycloneii_b17mux21\_primary.dat DCT\dctsim2\work\cycloneii_b17mux21\_primary.vhd DCT\dctsim2\work\cycloneii_b17mux21 DCT\dctsim2\work\cycloneii_b5mux21\verilog.asm DCT\dctsim2\work\cycloneii_b5mux21\_primary.dat DCT\dctsim2\work\cycloneii_b5mux21\_primary.vhd DCT\dctsim2\work\cycloneii_b5mux21 DCT\dctsim2\work\cycloneii_bmux21\verilog.asm DCT\dctsim2\work\cycloneii_bmux21\_primary.dat DCT\dctsim2\work\cycloneii_bmux21\_primary.vhd DCT\dctsim2\work\cycloneii_bmux21 DCT\dctsim2\work\cycloneii_clkctrl\verilog.asm DCT\dctsim2\work\cycloneii_clkctrl\_primary.dat DCT\dctsim2\work\cycloneii_clkctrl\_primary.vhd DCT\dctsim2\work\cycloneii_clkctrl DCT\dctsim2\work\cycloneii_clk_delay_cal_ctrl\verilog.asm DCT\dctsim2\work\cycloneii_clk_delay_cal_ctrl\_primary.dat DCT\dctsim2\work\cycloneii_clk_delay_cal_ctrl\_primary.vhd DCT\dctsim2\work\cycloneii_clk_delay_cal_ctrl DCT\dctsim2\work\cycloneii_clk_delay_ctrl\verilog.asm DCT\dctsim2\work\cycloneii_clk_delay_ctrl\_primary.dat DCT\dctsim2\work\cycloneii_clk_delay_ctrl\_primary.vhd DCT\dctsim2\work\cycloneii_clk_delay_ctrl DCT\dctsim2\work\cycloneii_crcblock\verilog.asm DCT\dctsim2\work\cycloneii_crcblock\_primary.dat DCT\dctsim2\work\cycloneii_crcblock\_primary.vhd DCT\dctsim2\work\cycloneii_crcblock DCT\dctsim2\work\cycloneii_dffe\verilog.asm DCT\dctsim2\work\cycloneii_dffe\_primary.dat DCT\dctsim2\work\cycloneii_dffe\_primary.vhd DCT\dctsim2\work\cycloneii_dffe DCT\dctsim2\work\cycloneii_ena_reg\verilog.asm DCT\dctsim2\work\cycloneii_ena_reg\_primary.dat DCT\dctsim2\work\cycloneii_ena_reg\_primary.vhd DCT\dctsim2\work\cycloneii_ena_reg DCT\dctsim2\work\cycloneii_io\verilog.asm DCT\dctsim2\work\cycloneii_io\_primary.dat DCT\dctsim2\work\cycloneii_io\_primary.vhd DCT\dctsim2\work\cycloneii_io DCT\dctsim2\work\cycloneii_jtag\verilog.asm DCT\dctsim2\work\cycloneii_jtag\_primary.dat DCT\dctsim2\work\cycloneii_jtag\_primary.vhd DCT\dctsim2\work\cycloneii_jtag DCT\dctsim2\work\cycloneii_latch\verilog.asm DCT\dctsim2\work\cycloneii_latch\_primary.dat DCT\dctsim2\work\cycloneii_latch\_primary.vhd DCT\dctsim2\work\cycloneii_latch DCT\dctsim2\work\cycloneii_lcell_comb\verilog.asm DCT\dctsim2\work\cycloneii_lcell_comb\_primary.dat DCT\dctsim2\work\cycloneii_lcell_comb\_primary.vhd DCT\dctsim2\work\cycloneii_lcell_comb DCT\dctsim2\work\cycloneii_lcell_ff\verilog.asm DCT\dctsim2\work\cycloneii_lcell_ff\_primary.dat DCT\dctsim2\work\cycloneii_lcell_ff\_primary.vhd DCT\dctsim2\work\cycloneii_lcell_ff DCT\dctsim2\work\cycloneii_mac_data_reg\verilog.asm DCT\dctsim2\work\cycloneii_mac_data_reg\_primary.dat DCT\dctsim2\work\cycloneii_mac_data_reg\_primary.vhd DCT\dctsim2\work\cycloneii_mac_data_reg DCT\dctsim2\work\cycloneii_mac_mult\verilog.asm DCT\dctsim2\work\cycloneii_mac_mult\_primary.dat DCT\dctsim2\work\cycloneii_mac_mult\_primary.vhd DCT\dctsim2\work\cycloneii_mac_mult DCT\dctsim2\work\cycloneii_mac_mult_internal\verilog.asm DCT\dctsim2\work\cycloneii_mac_mult_internal\_primary.dat DCT\dctsim2\work\cycloneii_mac_mult_internal\_primary.vhd DCT\dctsim2\work\cycloneii_mac_mult_internal DCT\dctsim2\work\cycloneii_mac_out\verilog.asm DCT\dctsim2\work\cycloneii_mac_out\_primary.dat DCT\dctsim2\work\cycloneii_mac_out\_primary.vhd DCT\dctsim2\work\cycloneii_mac_out DCT\dctsim2\work\cycloneii_mac_sign_reg\verilog.asm DCT\dctsim2\work\cycloneii_mac_sign_reg\_primary.dat DCT\dctsim2\work\cycloneii_mac_sign_reg\_primary.vhd DCT\dctsim2\work\cycloneii_mac_sign_reg DCT\dctsim2\work\cycloneii_mux21\verilog.asm DCT\dctsim2\work\cycloneii_mux21\_primary.dat DCT\dctsim2\work\cycloneii_mux21\_primary.vhd DCT\dctsim2\work\cycloneii_mux21 DCT\dctsim2\work\cycloneii_mux41\verilog.asm DCT\dctsim2\work\cycloneii_mux41\_primary.dat DCT\dctsim2\work\cycloneii_mux41\_primary.vhd DCT\dctsim2\work\cycloneii_mux41 DCT\dctsim2\work\cycloneii_m_cntr\verilog.asm DCT\dctsim2\work\cycloneii_m_cntr\_primary.dat DCT\dctsim2\work\cycloneii_m_cntr\_primary.vhd DCT\dctsim2\work\cycloneii_m_cntr DCT\dctsim2\work\cycloneii_nmux21\verilog.asm DCT\dctsim2\work\cycloneii_nmux21\_primary.dat DCT\dctsim2\work\cycloneii_nmux21\_primary.vhd DCT\dctsim2\work\cycloneii_nmux21 DCT\dctsim2\work\cycloneii_n_cntr\verilog.asm DCT\dctsim2\work\cycloneii_n_cntr\_primary.dat DCT\dctsim2\work\cycloneii_n_cntr\_primary.vhd DCT\dctsim2\work\cycloneii_n_cntr DCT\dctsim2\work\cycloneii_pll\verilog.asm DCT\dctsim2\work\cycloneii_pll\_primary.dat DCT\dctsim2\work\cycloneii_pll\_primary.vhd DCT\dctsim2\work\cycloneii_pll DCT\dctsim2\work\cycloneii_pll_reg\verilog.asm DCT\dctsim2\work\cycloneii_pll_reg\_primary.dat DCT\dctsim2\work\cycloneii_pll_reg\_primary.vhd DCT\dctsim2\work\cycloneii_pll_reg DCT\dctsim2\work\cycloneii_ram_block\verilog.asm DCT\dctsim2\work\cycloneii_ram_block\_primary.dat DCT\dctsim2\work\cycloneii_ram_block\_primary.vhd DCT\dctsim2\work\cycloneii_ram_block DCT\dctsim2\work\cycloneii_ram_pulse_generator\verilog.asm DCT\dctsim2\work\cycloneii_ram_pulse_generator\_primary.dat DCT\dctsim2\work\cycloneii_ram_pulse_generator\_primary.vhd DCT\dctsim2\work\cycloneii_ram_pulse_generator DCT\dctsim2\work\cycloneii_ram_register\verilog.asm DCT\dctsim2\work\cycloneii_ram_register\_primary.dat DCT\dctsim2\work\cycloneii_ram_register\_primary.vhd DCT\dctsim2\work\cycloneii_ram_register DCT\dctsim2\work\cycloneii_routing_wire\verilog.asm DCT\dctsim2\work\cycloneii_routing_wire\_primary.dat DCT\dctsim2\work\cycloneii_routing_wire\_primary.vhd DCT\dctsim2\work\cycloneii_routing_wire DCT\dctsim2\work\cycloneii_scale_cntr\verilog.asm DCT\dctsim2\work\cycloneii_scale_cntr\_primary.dat DCT\dctsim2\work\cycloneii_scale_cntr\_primary.vhd DCT\dctsim2\work\cycloneii_scale_cntr DCT\dctsim2\work\dct\verilog.asm DCT\dctsim2\work\dct\_primary.dat DCT\dctsim2\work\dct\_primary.vhd DCT\dctsim2\work\dct DCT\dctsim2\work\dctu\verilog.asm DCT\dctsim2\work\dctu\_primary.dat DCT\dctsim2\work\dctu\_primary.vhd DCT\dctsim2\work\dctu DCT\dctsim2\work\dctub\verilog.asm DCT\dctsim2\work\dctub\_primary.dat DCT\dctsim2\work\dctub\_primary.vhd DCT\dctsim2\work\dctub DCT\dctsim2\work\dct_mac\verilog.asm DCT\dctsim2\work\dct_mac\_primary.dat DCT\dctsim2\work\dct_mac\_primary.vhd DCT\dctsim2\work\dct_mac DCT\dctsim2\work\dct_syn\verilog.asm DCT\dctsim2\work\dct_syn\_primary.dat DCT\dctsim2\work\dct_syn\_primary.vhd DCT\dctsim2\work\dct_syn DCT\dctsim2\work\fdct\verilog.asm DCT\dctsim2\work\fdct\_primary.dat DCT\dctsim2\work\fdct\_primary.vhd DCT\dctsim2\work\fdct DCT\dctsim2\work\zigzag\verilog.asm DCT\dctsim2\work\zigzag\_primary.dat DCT\dctsim2\work\zigzag\_primary.vhd DCT\dctsim2\work\zigzag DCT\dctsim2\work\_info DCT\dctsim2\work DCT\dctsim2\zigzag.v DCT\dctsim2 DCT\dctu.bsf DCT\dctu.v DCT\dctub.bsf DCT\dctub.v DCT\dct_cos_table.v DCT\dct_mac.bsf DCT\dct_mac.v DCT\dct_syn.asm.rpt DCT\dct_syn.bsf DCT\dct_syn.done DCT\dct_syn.dpf DCT\dct_syn.eda.rpt DCT\dct_syn.fit.rpt DCT\dct_syn.fit.smsg DCT\dct_syn.fit.summary DCT\dct_syn.flow.rpt DCT\dct_syn.map.rpt DCT\dct_syn.map.summary DCT\dct_syn.pin DCT\dct_syn.pof DCT\dct_syn.qpf DCT\dct_syn.qsf DCT\dct_syn.qws DCT\dct_syn.sim.rpt DCT\dct_syn.sof DCT\dct_syn.tan.rpt DCT\dct_syn.tan.summary DCT\dct_syn.v DCT\dct_syn.vwf DCT\fdct.bsf DCT\fdct.v DCT\RTL VIEW.doc DCT\simulation\modelsim\dct_syn.vo DCT\simulation\modelsim\dct_syn.vo.bak DCT\simulation\modelsim\dct_syn_modelsim.xrf DCT\simulation\modelsim\dct_syn_v.sdo DCT\simulation\modelsim DCT\simulation DCT\transcript DCT\zigzag.bsf DCT\zigzag.v DCT\读我.txt DCT