文件名称:risc_cpu
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这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discr iption language and the design manner. This program have passed the Modelsim validate.
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discr iption language and the design manner. This program have passed the Modelsim validate.
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下载文件列表
压缩包 : 795978risc_cpu.rar 列表 test test\test.mpf test\cpu_register.v test\cpu_alu.v test\cpu_datactrl.v test\cpu_sctrl.v test\cpu_mem.v test\cpu_pcounter.v test\cpu_clkg.v test\cpu_top.v test\transcript test\cpu_admux.v test\vsim.wlf test\test.cr.mti test\work test\work\_info test\work\cpu_admux test\work\cpu_admux\_primary.vhd test\work\cpu_admux\verilog.asm test\work\cpu_admux\_primary.dat test\work\cpu_pcounter test\work\cpu_pcounter\_primary.vhd test\work\cpu_pcounter\verilog.asm test\work\cpu_pcounter\_primary.dat test\work\cpu_top test\work\cpu_top\_primary.vhd test\work\cpu_top\verilog.asm test\work\cpu_top\_primary.dat test\work\cpu_clkg test\work\cpu_clkg\_primary.vhd test\work\cpu_clkg\verilog.asm test\work\cpu_clkg\_primary.dat test\work\cpu_mem test\work\cpu_mem\_primary.vhd test\work\cpu_mem\verilog.asm test\work\cpu_mem\_primary.dat test\work\cpu_sctrl test\work\cpu_sctrl\_primary.vhd test\work\cpu_sctrl\verilog.asm test\work\cpu_sctrl\_primary.dat test\work\cpu_datactrl test\work\cpu_datactrl\_primary.vhd test\work\cpu_datactrl\verilog.asm test\work\cpu_datactrl\_primary.dat test\work\cpu_alu test\work\cpu_alu\_primary.vhd test\work\cpu_alu\verilog.asm test\work\cpu_alu\_primary.dat test\work\cpu_register test\work\cpu_register\_primary.vhd test\work\cpu_register\verilog.asm test\work\cpu_register\_primary.dat test\work\@f@i@r@filter_1 test\work\@f@i@r@filter_1\_primary.vhd test\work\@f@i@r@filter_1\verilog.asm test\work\@f@i@r@filter_1\_primary.dat test\work\my@test test\work\my@test\_primary.vhd test\work\my@test\verilog.asm test\work\my@test\_primary.dat