文件名称:testuart2
- 所属分类：
- 串口编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2008-10-13
- 文件大小：
- 348.67kb
- 下载次数：
- 0次
- 提 供 者：
- yangzh******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog语言，硬件调试，用于actel刚推出的fusion系列芯片的接口调试
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 73462695testuart2.rar 列表 testuart2\smartgen\smartgen.aws testuart2\smartgen testuart2\hdl\rec.v testuart2\hdl\send.v testuart2\hdl\uart_test.v testuart2\hdl testuart2\constraint testuart2\viewdraw\viewdraw.ini testuart2\viewdraw\vf\project.lst testuart2\viewdraw\vf testuart2\viewdraw\sch testuart2\viewdraw\sym testuart2\viewdraw\wir testuart2\viewdraw testuart2\component testuart2\coreconsole testuart2\simulation\modelsim.ini testuart2\simulation testuart2\synthesis\uart_test_syn.prj testuart2\synthesis\stdout.log testuart2\synthesis\syntmp\uart_test_flink.htm testuart2\synthesis\syntmp\uart_test_srr.htm testuart2\synthesis\syntmp\uart_test_toc.htm testuart2\synthesis\syntmp\sap.log testuart2\synthesis\syntmp\uart_test.plg testuart2\synthesis\syntmp testuart2\synthesis\backup testuart2\synthesis\run_options.txt testuart2\synthesis\uart_test.srr testuart2\synthesis\uart_test.htm testuart2\synthesis\uart_test.tlg testuart2\synthesis\uart_test.srs testuart2\synthesis\uart_test.sap testuart2\synthesis\uart_test.fse testuart2\synthesis\traplog.tlg testuart2\synthesis\.recordref testuart2\synthesis\uart_test.srd testuart2\synthesis\uart_test.srm testuart2\synthesis\uart_test.map testuart2\synthesis\uart_test.edn testuart2\synthesis\uart_test.sdf testuart2\synthesis\uart_test_sdc.sdc testuart2\synthesis\uart_test.so testuart2\synthesis\uart_test.areasrr testuart2\synthesis\uart_test_drc.rpt testuart2\synthesis testuart2\phy_synthesis testuart2\stimulus testuart2\designer\impl1\simulation testuart2\designer\impl1\uart_test.tcl testuart2\designer\impl1\designer_genhdl.log testuart2\designer\impl1\uart_test.ide_des testuart2\designer\impl1\uart_test.dtf\verify.log testuart2\designer\impl1\uart_test.dtf testuart2\designer\impl1\uart_test_ba.sdf testuart2\designer\impl1\uart_test_ba.v testuart2\designer\impl1\uart_test.pdb testuart2\designer\impl1\uart_test.pdb.depends testuart2\designer\impl1\uart_test.adb testuart2\designer\impl1\designer.log testuart2\designer\impl1\uart_test_fp\uart_test.pro testuart2\designer\impl1\uart_test_fp\$$FlashPro_FPBBALTLPT1.L$$ testuart2\designer\impl1\uart_test_fp\projectData\uart_test.pdb testuart2\designer\impl1\uart_test_fp\projectData testuart2\designer\impl1\uart_test_fp\uart_test.log testuart2\designer\impl1\uart_test_fp testuart2\designer\impl1 testuart2\designer testuart2\testuart2.prj testuart2