文件名称:Example-4-1
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程序补充说明：对于时序逻辑，即always模块的敏感表为沿敏感信号（多为时钟或复位的正沿或负沿），统一使用非阻塞赋值“<=”
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下载文件列表
压缩包 : 7941958example-4-1.rar 列表 Example-4-1\cnt.prd Example-4-1\cnt.prj Example-4-1\示例说明.doc Example-4-1\source\cnt1.v Example-4-1\source\cnt2.v Example-4-1\source\cnt3.v Example-4-1\source\syntmp.msg Example-4-1\rev_1\cnt1.edf Example-4-1\rev_1\cnt1.fse Example-4-1\rev_1\cnt1.srm Example-4-1\rev_1\cnt1.srr Example-4-1\rev_1\cnt1.srs Example-4-1\rev_1\cnt1.tlg Example-4-1\rev_1\cnt2.edf Example-4-1\rev_1\cnt2.fse Example-4-1\rev_1\cnt2.srm Example-4-1\rev_1\cnt2.srr Example-4-1\rev_1\cnt2.srs Example-4-1\rev_1\cnt2.tlg Example-4-1\rev_1\cnt3.edf Example-4-1\rev_1\cnt3.fse Example-4-1\rev_1\cnt3.srm Example-4-1\rev_1\cnt3.srr Example-4-1\rev_1\cnt3.srs Example-4-1\rev_1\cnt3.tlg Example-4-1\rev_1\syntmp\cnt1.plg Example-4-1\rev_1\syntmp\cnt2.msg Example-4-1\rev_1\syntmp\cnt2.plg Example-4-1\rev_1\syntmp\cnt3.msg Example-4-1\rev_1\syntmp\cnt3.plg Example-4-1\rev_1\syntmp Example-4-1\rev_1\par_1 Example-4-1\source Example-4-1\rev_1 Example-4-1