文件名称:Verilog_sourcecode
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清华大学verilog hdl源码例子，作业，内含源代码，详细的文档说明，非常有用
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压缩包 : 119128639verilog_sourcecode.rar 列表 Verilog源码例子\iic\ISE\iic\.untf Verilog源码例子\iic\ISE\iic\automake.log Verilog源码例子\iic\ISE\iic\bitgen.ut Verilog源码例子\iic\ISE\iic\coregen.log Verilog源码例子\iic\ISE\iic\coregen.prj Verilog源码例子\iic\ISE\iic\i2c.bgn Verilog源码例子\iic\ISE\iic\i2c.bit Verilog源码例子\iic\ISE\iic\i2c.bld Verilog源码例子\iic\ISE\iic\i2c.cmd_log Verilog源码例子\iic\ISE\iic\i2c.drc Verilog源码例子\iic\ISE\iic\i2c.lfp Verilog源码例子\iic\ISE\iic\i2c.lso Verilog源码例子\iic\ISE\iic\i2c.mrp Verilog源码例子\iic\ISE\iic\i2c.nc1 Verilog源码例子\iic\ISE\iic\i2c.ncd Verilog源码例子\iic\ISE\iic\i2c.ngc Verilog源码例子\iic\ISE\iic\i2c.ngd Verilog源码例子\iic\ISE\iic\i2c.ngm Verilog源码例子\iic\ISE\iic\i2c.ngr Verilog源码例子\iic\ISE\iic\i2c.pad Verilog源码例子\iic\ISE\iic\i2c.pad_txt Verilog源码例子\iic\ISE\iic\i2c.par Verilog源码例子\iic\ISE\iic\i2c.pcf Verilog源码例子\iic\ISE\iic\i2c.placed_ncd_tracker Verilog源码例子\iic\ISE\iic\i2c.prj Verilog源码例子\iic\ISE\iic\i2c.routed_ncd_tracker Verilog源码例子\iic\ISE\iic\i2c.stx Verilog源码例子\iic\ISE\iic\i2c.syr Verilog源码例子\iic\ISE\iic\i2c.twr Verilog源码例子\iic\ISE\iic\i2c.twx Verilog源码例子\iic\ISE\iic\i2c.ucf Verilog源码例子\iic\ISE\iic\i2c.ucf.untf Verilog源码例子\iic\ISE\iic\i2c.ut Verilog源码例子\iic\ISE\iic\i2c.v Verilog源码例子\iic\ISE\iic\i2c.xpi Verilog源码例子\iic\ISE\iic\i2c_clk.v Verilog源码例子\iic\ISE\iic\i2c_last_par.ncd Verilog源码例子\iic\ISE\iic\i2c_map.ncd Verilog源码例子\iic\ISE\iic\i2c_map.ngm Verilog源码例子\iic\ISE\iic\i2c_pad.csv Verilog源码例子\iic\ISE\iic\i2c_pad.txt Verilog源码例子\iic\ISE\iic\i2c_st.v Verilog源码例子\iic\ISE\iic\i2c_st.v.bak Verilog源码例子\iic\ISE\iic\i2c_vhdl.prj Verilog源码例子\iic\ISE\iic\iic.dhp Verilog源码例子\iic\ISE\iic\iic.npl Verilog源码例子\iic\ISE\iic\_impact.cmd Verilog源码例子\iic\ISE\iic\_impact.log Verilog源码例子\iic\ISE\iic\__projnav.log Verilog源码例子\iic\ISE\iic\xst\work\hdllib.ref Verilog源码例子\iic\ISE\iic\xst\work\vlg1E\i2c.bin Verilog源码例子\iic\ISE\iic\xst\work\vlg20\i2c_st.bin Verilog源码例子\iic\ISE\iic\xst\work\vlg53\i2c_clk.bin Verilog源码例子\iic\ISE\iic\_ngo\netlist.lst Verilog源码例子\iic\ISE\iic\__projnav\bitgen.rsp Verilog源码例子\iic\ISE\iic\__projnav\coregen.rsp Verilog源码例子\iic\ISE\iic\__projnav\ednTOngd_tcl.rsp Verilog源码例子\iic\ISE\iic\__projnav\i2c.xst Verilog源码例子\iic\ISE\iic\__projnav\i2c_ncdTOut_tcl.rsp Verilog源码例子\iic\ISE\iic\__projnav\iic.gfl Verilog源码例子\iic\ISE\iic\__projnav\iic_flowplus.gfl Verilog源码例子\iic\ISE\iic\__projnav\map.log Verilog源码例子\iic\ISE\iic\__projnav\nc1TOncd_tcl.rsp Verilog源码例子\iic\ISE\iic\__projnav\par.log Verilog源码例子\iic\ISE\iic\__projnav\parentAssignPackagePinsApp_tcl.rsp Verilog源码例子\iic\ISE\iic\__projnav\posttrc.log Verilog源码例子\iic\ISE\iic\__projnav\runXst_tcl.rsp Verilog源码例子\iic\RTL\i2c.v Verilog源码例子\iic\RTL\i2c.v.bak Verilog源码例子\iic\RTL\i2c_clk.v Verilog源码例子\iic\RTL\i2c_st.bak Verilog源码例子\iic\RTL\i2c_st.v Verilog源码例子\iic\RTL\BACK\clk_rst.v Verilog源码例子\iic\RTL\BACK\i2c.v Verilog源码例子\iic\RTL\BACK\i2c.v.bak Verilog源码例子\iic\RTL\BACK\i2c_clk.v Verilog源码例子\iic\RTL\BACK\i2c_clk.v.bak Verilog源码例子\iic\RTL\BACK\i2c_rreg.v Verilog源码例子\iic\RTL\BACK\i2c_st.v Verilog源码例子\iic\RTL\BACK\i2c_st.v.bak Verilog源码例子\iic\RTL\BACK\i2c_tbuf.v Verilog源码例子\iic\RTL\BACK\i2c_tbuf.v.bak Verilog源码例子\iic\RTL\BACK\i2c_wreg.v Verilog源码例子\lcm\ISE\LCM\.untf Verilog源码例子\lcm\ISE\LCM\automake.log Verilog源码例子\lcm\ISE\LCM\bitgen.ut Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bgn Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bit Verilog源码例子\lcm\ISE\LCM\fpga_lcm.bld Verilog源码例子\lcm\ISE\LCM\fpga_lcm.cmd_log Verilog源码例子\lcm\ISE\LCM\fpga_lcm.drc Verilog源码例子\lcm\ISE\LCM\fpga_lcm.lfp Verilog源码例子\lcm\ISE\LCM\fpga_lcm.lso Verilog源码例子\lcm\ISE\LCM\fpga_lcm.mrp Verilog源码例子\lcm\ISE\LCM\fpga_lcm.nc1 Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ncd Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngc Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngd Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngm Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ngr Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pad Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pad_txt Verilog源码例子\lcm\ISE\LCM\fpga_lcm.par Verilog源码例子\lcm\ISE\LCM\fpga_lcm.pcf Verilog源码例子\lcm\ISE\LCM\fpga_lcm.placed_ncd_tracker Verilog源码例子\lcm\ISE\LCM\fpga_lcm.prj Verilog源码例子\lcm\ISE\LCM\fpga_lcm.routed_ncd_tracker Verilog源码例子\lcm\ISE\LCM\fpga_lcm.stx Verilog源码例子\lcm\ISE\LCM\fpga_lcm.syr Verilog源码例子\lcm\ISE\LCM\fpga_lcm.twr Verilog源码例子\lcm\ISE\LCM\fpga_lcm.twx Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ucf Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ucf.untf Verilog源码例子\lcm\ISE\LCM\fpga_lcm.ut Verilog源码例子\lcm\ISE\LCM\fpga_lcm.v Verilog源码例子\lcm\ISE\LCM\fpga_lcm.xpi Verilog源码例子\lcm\ISE\LCM\fpga_lcm_last_par.ncd Verilog源码例子\lcm\ISE\LCM\fpga_lcm_map.ncd Verilog源码例子\lcm\ISE\LCM\fpga_lcm_map.ngm Verilog源码例子\lcm\ISE\LCM\fpga_lcm_pad.csv Verilog源码例子\lcm\ISE\LCM\fpga_lcm_pad.txt Verilog源码例子\lcm\ISE\LCM\fpga_lcm_vhdl.prj Verilog源码例子\lcm\ISE\LCM\LCM.dhp Verilog源码例子\lcm\ISE\LCM\LCM.npl Verilog源码例子\lcm\ISE\LCM\lcm.v Verilog源码例子\lcm\ISE\LCM\rom_32x8.bgn Verilog源码例子\lcm\ISE\LCM\rom_32x8.bit Verilog源码例子\lcm\ISE\LCM\rom_32x8.bld Verilog源码例子\lcm\ISE\LCM\rom_32x8.cmd_log Verilog源码例子\lcm\ISE\LCM\rom_32x8.drc Verilog源码例子\lcm\ISE\LCM\rom_32x8.lso Verilog源码例子\lcm\ISE\LCM\rom_32x8.mrp Verilog源码例子\lcm\ISE\LCM\rom_32x8.nc1 Verilog源码例子\lcm\ISE\LCM\rom_32x8.ncd Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngc Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngd Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngm Verilog源码例子\lcm\ISE\LCM\rom_32x8.ngr Verilog源码例子\lcm\ISE\LCM\rom_32x8.pad Verilog源码例子\lcm\ISE\LCM\rom_32x8.pad_txt Verilog源码例子\lcm\ISE\LCM\rom_32x8.par Verilog源码例子\lcm\ISE\LCM\rom_32x8.pcf Verilog源码例子\lcm\ISE\LCM\rom_32x8.placed_ncd_tracker Verilog源码例子\lcm\ISE\LCM\rom_32x8.prj Verilog源码例子\lcm\ISE\LCM\rom_32x8.routed_ncd_tracker Verilog源码例子\lcm\ISE\LCM\rom_32x8.stx Verilog源码例子\lcm\ISE\LCM\rom_32x8.syr Verilog源码例子\lcm\ISE\LCM\rom_32x8.twr Verilog源码例子\lcm\ISE\LCM\rom_32x8.twx Verilog源码例子\lcm\ISE\LCM\rom_32x8.ucf Verilog源码例子\lcm\ISE\LCM\rom_32x8.ut Verilog源码例子\lcm\ISE\LCM\rom_32x8.v Verilog源码例子\lcm\ISE\LCM\rom_32x8.xpi Verilog源码例子\lcm\ISE\LCM\rom_32x8_map.ncd Verilog源码例子\lcm\ISE\LCM\rom_32x8_map.ngm Verilog源码例子\lcm\ISE\LCM\rom_32x8_pad.csv Verilog源码例子\lcm\ISE\LCM\rom_32x8_pad.txt Verilog源码例子\lcm\ISE\LCM\rom_32x8_vhdl.prj Verilog源码例子\lcm\ISE\LCM\__projnav.log Verilog源码例子\lcm\ISE\LCM\xst\work\hdllib.ref Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4A\rom_32x8.bin Verilog源码例子\lcm\ISE\LCM\xst\work\vlg4D\fpga_lcm.bin Verilog源码例子\lcm\ISE\LCM\xst\work\vlg68\lcm.bin Verilog源码例子\lcm\ISE\LCM\_ngo\netlist.lst Verilog源码例子\lcm\ISE\LCM\__projnav\ad.gfl Verilog源码例子\lcm\ISE\LCM\__projnav\bitgen.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\ednTOngd_tcl.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\fpga_lcm.xst Verilog源码例子\lcm\ISE\LCM\__projnav\fpga_lcm_ncdTOut_tcl.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\LCM.gfl Verilog源码例子\lcm\ISE\LCM\__projnav\LCM_flowplus.gfl Verilog源码例子\lcm\ISE\LCM\__projnav\map.log Verilog源码例子\lcm\ISE\LCM\__projnav\nc1TOncd_tcl.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\par.log Verilog源码例子\lcm\ISE\LCM\__projnav\parentAssignPackagePinsApp_tcl.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\posttrc.log Verilog源码例子\lcm\ISE\LCM\__projnav\rom_32x8.xst Verilog源码例子\lcm\ISE\LCM\__projnav\rom_32x8_ncdTOut_tcl.rsp Verilog源码例子\lcm\ISE\LCM\__projnav\runXst_tcl.rsp Verilog源码例子\lcm\RTL\fpga_lcm.v Verilog源码例子\lcm\RTL\lcm.v Verilog源码例子\lcm\RTL\rom_32x8.v Verilog源码例子\rs232\ISE\rs23240x\automake.log Verilog源码例子\rs232\ISE\rs23240x\bitgen.ut Verilog源码例子\rs232\ISE\rs23240x\diag.v Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.bgn Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.bit Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.bld Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.cmd_log Verilog源码例子\rs232\ISE\rs23240x\fpga_40rs232.drc Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.lso Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.mrp Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.nc1 Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ncd Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngc Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngd Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngm Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ngr Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pad Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pad_txt Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.par Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.pcf Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.placed_ncd_tracker Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.prj Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.routed_ncd_tracker Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.stx Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.syr Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.twr Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.twx Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.ut Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232.xpi Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_last_par.ncd Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_map.ncd Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_map.ngm Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_pad.csv Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_pad.txt Verilog源码例子\rs232\ISE\rs23240x\fpga_40RS232_vhdl.prj Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.ucf Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.ucf.untf Verilog源码例子\rs232\ISE\rs23240x\fpga_40XRS232.v Verilog源码例子\rs232\ISE\rs23240x\rs23240x.dhp Verilog源码例子\rs232\ISE\rs23240x\rs23240x.npl Verilog源码例子\rs232\ISE\rs23240x\serial.v Verilog源码例子\rs232\ISE\rs23240x\__projnav.log Verilog源码例子\rs232\ISE\rs23240x\xst\work\hdllib.ref Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg20\serial.bin Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg25\fpga_40RS232.bin Verilog源码例子\rs232\ISE\rs23240x\xst\work\vlg61\diag.bin Verilog源码例子\rs232\ISE\rs23240x\_ngo\netlist.lst Verilog源码例子\rs232\ISE\rs23240x\__projnav\bitgen.rsp Verilog源码例子\rs232\ISE\rs23240x\__projnav\ednTOngd_tcl.rsp Verilog源码例子\rs232\ISE\rs23240x\__projnav\fpga_40RS232.xst Verilog源码例子\rs232\ISE\rs23240x\__projnav\fpga_40RS232_ncdTOut_tcl.rsp Verilog源码例子\rs232\ISE\rs23240x\__projnav\map.log Verilog源码例子\rs232\ISE\rs23240x\__projnav\nc1TOncd_tcl.rsp Verilog源码例子\rs232\ISE\rs23240x\__projnav\par.log Verilog源码例子\rs232\ISE\rs23240x\__projnav\posttrc.log Verilog源码例子\rs232\ISE\rs23240x\__projnav\rs23240x.gfl Verilog源码例子\rs232\ISE\rs23240x\__projnav\rs23240x_flowplus.gfl Verilog源码例子\rs232\ISE\rs23240x\__projnav\runXst_tcl.rsp Verilog源码例子\rs232\rtl\diag.v Verilog源码例子\rs232\rtl\fpga_40XRS232.ucf Verilog源码例子\rs232\rtl\fpga_40XRS232.ucf.bak Verilog源码例子\rs232\rtl\fpga_40XRS232.v Verilog源码例子\rs232\rtl\fpga_40XRS232.v.bak Verilog源码例子\rs232\rtl\serial.v Verilog源码例子\adder\ise\adder\.untf Verilog源码例子\adder\ise\adder\adder.bgn Verilog源码例子\adder\ise\adder\adder.bit Verilog源码例子\adder\ise\adder\adder.bld Verilog源码例子\adder\ise\adder\adder.cmd_log Verilog源码例子\adder\ise\adder\adder.dhp Verilog源码例子\adder\ise\adder\adder.drc Verilog源码例子\adder\ise\adder\adder.lfp Verilog源码例子\adder\ise\adder\adder.lso Verilog源码例子\adder\ise\adder\adder.mrp Verilog源码例子\adder\ise\adder\adder.nc1 Verilog源码例子\adder\ise\adder\adder.ncd Verilog源码例子\adder\ise\adder\adder.ngc Verilog源码例子\adder\ise\adder\adder.ngd Verilog源码例子\adder\ise\adder\adder.ngm Verilog源码例子\adder\ise\adder\adder.ngr Verilog源码例子\adder\ise\adder\adder.npl Verilog源码例子\adder\ise\adder\adder.pad Verilog源码例子\adder\ise\adder\adder.pad_txt Verilog源码例子\adder\ise\adder\adder.par Verilog源码例子\adder\ise\adder\adder.pcf Verilog源码例子\adder\ise\adder\adder.placed_ncd_tracker Verilog源码例子\adder\ise\adder\adder.prj Verilog源码例子\adder\ise\adder\adder.routed_ncd_tracker Verilog源码例子\adder\ise\adder\adder.stx Verilog源码例子\adder\ise\adder\adder.syr Verilog源码例子\adder\ise\adder\adder.twr Verilog源码例子\adder\ise\adder\adder.twx Verilog源码例子\adder\ise\adder\adder.ucf Verilog源码例子\adder\ise\adder\adder.ucf.untf Verilog源码例子\adder\ise\adder\adder.ut Verilog源码例子\adder\ise\adder\adder.v Verilog源码例子\adder\ise\adder\adder.xpi Verilog源码例子\adder\ise\adder\adder_map.ncd Verilog源码例子\adder\ise\adder\adder_map.ngm Verilog源码例子\adder\ise\adder\adder_pad.csv Verilog源码例子\adder\ise\adder\adder_pad.txt Verilog源码例子\adder\ise\adder\adder_vhdl.prj Verilog源码例子\adder\ise\adder\automake.log Verilog源码例子\adder\ise\adder\bitgen.ut Verilog源码例子\adder\ise\adder\__projnav.log Verilog源码例子\adder\ise\adder\xst\work\hdllib.ref Verilog源码例子\adder\ise\adder\xst\work\vlg54\adder.bin Verilog源码例子\adder\ise\adder\_ngo\netlist.lst Verilog源码例子\adder\ise\adder\__projnav\adder.gfl Verilog源码例子\adder\ise\adder\__projnav\adder.xst Verilog源码例子\adder\ise\adder\__projnav\adder_flowplus.gfl Verilog源码例子\adder\ise\adder\__projnav\adder_ncdTOut_tcl.rsp Verilog源码例子\adder\ise\adder\__projnav\bitgen.rsp Verilog源码例子\adder\ise\adder\__projnav\ednTOngd_tcl.rsp Verilog源码例子\adder\ise\adder\__projnav\map.log Verilog源码例子\adder\ise\adder\__projnav\nc1TOncd_tcl.rsp Verilog源码例子\adder\ise\adder\__projnav\par.log Verilog源码例子\adder\ise\adder\__projnav\parentAssignPackagePinsApp_tcl.rsp Verilog源码例子\adder\ise\adder\__projnav\posttrc.log Verilog源码例子\adder\ise\adder\__projnav\runXst_tcl.rsp Verilog源码例子\adder\modelsim\adder.cr.mti Verilog源码例子\adder\modelsim\adder.mpf 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