压缩包 : 9927422fpga.rar 列表
fpga\使用说明.txt
fpga\Chapter9 Sample\使用说明.txt
fpga\Chapter9 Sample\canbus\.untf
fpga\Chapter9 Sample\canbus\can_acf.v
fpga\Chapter9 Sample\canbus\can_bsp.v
fpga\Chapter9 Sample\canbus\can_btl.v
fpga\Chapter9 Sample\canbus\can_crc.v
fpga\Chapter9 Sample\canbus\can_defines.v
fpga\Chapter9 Sample\canbus\can_fifo.cmd_log
fpga\Chapter9 Sample\canbus\can_fifo.lso
fpga\Chapter9 Sample\canbus\can_fifo.ngc
fpga\Chapter9 Sample\canbus\can_fifo.ngr
fpga\Chapter9 Sample\canbus\can_fifo.prj
fpga\Chapter9 Sample\canbus\can_fifo.stx
fpga\Chapter9 Sample\canbus\can_fifo.syr
fpga\Chapter9 Sample\canbus\can_fifo.v
fpga\Chapter9 Sample\canbus\can_fifo_vhdl.prj
fpga\Chapter9 Sample\canbus\can_ibo.v
fpga\Chapter9 Sample\canbus\can_register.v
fpga\Chapter9 Sample\canbus\can_register_asyn.v
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.cmd_log
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.lso
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.ngc
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.ngr
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.prj
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.stx
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.syr
fpga\Chapter9 Sample\canbus\can_register_asyn_syn.v
fpga\Chapter9 Sample\canbus\can_register_asyn_syn_vhdl.prj
fpga\Chapter9 Sample\canbus\can_register_syn.v
fpga\Chapter9 Sample\canbus\can_registers.lso
fpga\Chapter9 Sample\canbus\can_registers.prj
fpga\Chapter9 Sample\canbus\can_registers.stx
fpga\Chapter9 Sample\canbus\can_registers.v
fpga\Chapter9 Sample\canbus\can_registers_vhdl.prj
fpga\Chapter9 Sample\canbus\can_testbench.fdo
fpga\Chapter9 Sample\canbus\can_testbench.ndo
fpga\Chapter9 Sample\canbus\can_testbench.udo
fpga\Chapter9 Sample\canbus\can_testbench.v
fpga\Chapter9 Sample\canbus\can_testbench_defines.v
fpga\Chapter9 Sample\canbus\can_top.bld
fpga\Chapter9 Sample\canbus\can_top.cmd_log
fpga\Chapter9 Sample\canbus\can_top.ldo
fpga\Chapter9 Sample\canbus\can_top.lso
fpga\Chapter9 Sample\canbus\can_top.ngc
fpga\Chapter9 Sample\canbus\can_top.ngd
fpga\Chapter9 Sample\canbus\can_top.ngr
fpga\Chapter9 Sample\canbus\can_top.prj
fpga\Chapter9 Sample\canbus\can_top.stx
fpga\Chapter9 Sample\canbus\can_top.syr
fpga\Chapter9 Sample\canbus\can_top.v
fpga\Chapter9 Sample\canbus\can_top.vhdsim_xlate
fpga\Chapter9 Sample\canbus\can_top.xlate_nlf
fpga\Chapter9 Sample\canbus\can_top_translate.nlf
fpga\Chapter9 Sample\canbus\can_top_translate.vhd
fpga\Chapter9 Sample\canbus\can_top_vhdl.prj
fpga\Chapter9 Sample\canbus\canbus.dhp
fpga\Chapter9 Sample\canbus\canbus.npl
fpga\Chapter9 Sample\canbus\coregen.prj
fpga\Chapter9 Sample\canbus\prjname.lso
fpga\Chapter9 Sample\canbus\timescale.v
fpga\Chapter9 Sample\canbus\transcript
fpga\Chapter9 Sample\canbus\__projnav\can_fifo.xst
fpga\Chapter9 Sample\canbus\__projnav\can_register_asyn_syn.xst
fpga\Chapter9 Sample\canbus\__projnav\can_registers.xst
fpga\Chapter9 Sample\canbus\__projnav\can_top.xst
fpga\Chapter9 Sample\canbus\__projnav\canbus.gfl
fpga\Chapter9 Sample\canbus\__projnav\canbus_flowplus.gfl
fpga\Chapter9 Sample\canbus\__projnav\coregen.rsp
fpga\Chapter9 Sample\canbus\__projnav\ednTOngd_tcl.rsp
fpga\Chapter9 Sample\canbus\__projnav\runXst_tcl.rsp
fpga\Chapter9 Sample\canbus\__projnav\xst_sprjTOstx_tcl.rsp
fpga\Chapter9 Sample\canbus\_ngo\netlist.lst
fpga\Chapter9 Sample\canbus\work\_info
fpga\Chapter9 Sample\canbus\work\can_acf\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_acf\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_acf\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_bsp\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_bsp\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_bsp\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_btl\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_btl\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_btl\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_crc\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_crc\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_crc\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_fifo\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_fifo\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_fifo\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_ibo\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_ibo\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_ibo\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_register\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_register\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_register\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_register_asyn\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_register_asyn\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_register_asyn\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_register_asyn_syn\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_register_asyn_syn\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_register_asyn_syn\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_registers\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_registers\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_registers\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_testbench\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_testbench\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_testbench\verilog.asm
fpga\Chapter9 Sample\canbus\work\can_top\_primary.dat
fpga\Chapter9 Sample\canbus\work\can_top\_primary.vhd
fpga\Chapter9 Sample\canbus\work\can_top\verilog.asm
fpga\Chapter9 Sample\canbus\work\glbl\_primary.dat
fpga\Chapter9 Sample\canbus\work\glbl\_primary.vhd
fpga\Chapter9 Sample\canbus\work\glbl\verilog.asm
fpga\Chapter9 Sample\canbus\xst\work\hdllib.ref
fpga\Chapter9 Sample\canbus\xst\work\vlg01\can_fifo.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg1B\can_ibo.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg31\can_register_asyn_syn.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg42\can_bsp.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg43\can_btl.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg48\can_register_asyn.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg49\can_crc.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg49\can_registers.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg4F\can_acf.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg5E\can_register.bin
fpga\Chapter9 Sample\canbus\xst\work\vlg70\can_top.bin
fpga\Chapter8 Sample\使用说明.txt
fpga\Chapter8 Sample\vga\coregen.prj
fpga\Chapter8 Sample\vga\generic_dpram.v
fpga\Chapter8 Sample\vga\generic_spram.v
fpga\Chapter8 Sample\vga\prjname.lso
fpga\Chapter8 Sample\vga\sync_check.v
fpga\Chapter8 Sample\vga\test_bench_top.v
fpga\Chapter8 Sample\vga\tests.v
fpga\Chapter8 Sample\vga\timescale.v
fpga\Chapter8 Sample\vga\vga.dhp
fpga\Chapter8 Sample\vga\vga.npl
fpga\Chapter8 Sample\vga\vga_clkgen.v
fpga\Chapter8 Sample\vga\vga_colproc.v
fpga\Chapter8 Sample\vga\vga_csm_pb.v
fpga\Chapter8 Sample\vga\vga_cur_cregs.v
fpga\Chapter8 Sample\vga\vga_curproc.v
fpga\Chapter8 Sample\vga\vga_defines.v
fpga\Chapter8 Sample\vga\vga_enh_top.cmd_log
fpga\Chapter8 Sample\vga\vga_enh_top.lso
fpga\Chapter8 Sample\vga\vga_enh_top.prj
fpga\Chapter8 Sample\vga\vga_enh_top.stx
fpga\Chapter8 Sample\vga\vga_enh_top.syr
fpga\Chapter8 Sample\vga\vga_enh_top.v
fpga\Chapter8 Sample\vga\vga_enh_top_vhdl.prj
fpga\Chapter8 Sample\vga\vga_fifo.v
fpga\Chapter8 Sample\vga\vga_fifo_dc.v
fpga\Chapter8 Sample\vga\vga_pgen.v
fpga\Chapter8 Sample\vga\vga_tgen.v
fpga\Chapter8 Sample\vga\vga_vtim.v
fpga\Chapter8 Sample\vga\vga_wb_master.v
fpga\Chapter8 Sample\vga\vga_wb_slave.v
fpga\Chapter8 Sample\vga\wb_b3_check.v
fpga\Chapter8 Sample\vga\wb_mast_model.v
fpga\Chapter8 Sample\vga\wb_model_defines.v
fpga\Chapter8 Sample\vga\wb_slv_model.v
fpga\Chapter8 Sample\vga\__projnav\coregen.rsp
fpga\Chapter8 Sample\vga\__projnav\runXst_tcl.rsp
fpga\Chapter8 Sample\vga\__projnav\vga.gfl
fpga\Chapter8 Sample\vga\__projnav\vga_enh_top.xst
fpga\Chapter8 Sample\vga\__projnav\vga_flowplus.gfl
fpga\Chapter8 Sample\vga\__projnav\xst_sprjTOstx_tcl.rsp
fpga\Chapter8 Sample\vga\xst\work\hdllib.ref
fpga\Chapter8 Sample\vga\xst\work\vlg04\vga_wb_slave.bin
fpga\Chapter8 Sample\vga\xst\work\vlg05\vga_wb_master.bin
fpga\Chapter8 Sample\vga\xst\work\vlg07\vga_fifo_dc.bin
fpga\Chapter8 Sample\vga\xst\work\vlg07\vga_pgen.bin
fpga\Chapter8 Sample\vga\xst\work\vlg34\generic_dpram.bin
fpga\Chapter8 Sample\vga\xst\work\vlg4D\vga_csm_pb.bin
fpga\Chapter8 Sample\vga\xst\work\vlg4D\vga_vtim.bin
fpga\Chapter8 Sample\vga\xst\work\vlg53\generic_spram.bin
fpga\Chapter8 Sample\vga\xst\work\vlg59\vga_clkgen.bin
fpga\Chapter8 Sample\vga\xst\work\vlg5D\vga_fifo.bin
fpga\Chapter8 Sample\vga\xst\work\vlg5F\vga_colproc.bin
fpga\Chapter8 Sample\vga\xst\work\vlg6A\vga_enh_top.bin
fpga\Chapter8 Sample\vga\xst\work\vlg7B\vga_tgen.bin
fpga\Chapter7 Sample\LWBBUSCHANGE.v
fpga\Chapter7 Sample\LWBDECODE.v
fpga\Chapter7 Sample\LWBSAA7113.v
fpga\Chapter7 Sample\LWBSRAM.v
fpga\Chapter7 Sample\timescale.v
fpga\Chapter7 Sample\tst_saa7113.v
fpga\Chapter7 Sample\使用说明.txt
fpga\Chapter6 Sample\使用说明.txt
fpga\Chapter6 Sample\USB\Application\Cube.aps
fpga\Chapter6 Sample\USB\Application\Cube.rc
fpga\Chapter6 Sample\USB\Application\InputDialog.cpp
fpga\Chapter6 Sample\USB\Application\InputDialog.h
fpga\Chapter6 Sample\USB\Application\SoftLock.cpp
fpga\Chapter6 Sample\USB\Application\SoftLock.h
fpga\Chapter6 Sample\USB\Application\cube.clw
fpga\Chapter6 Sample\USB\Application\cube.cpp
fpga\Chapter6 Sample\USB\Application\cube.dsp
fpga\Chapter6 Sample\USB\Application\cube.dsw
fpga\Chapter6 Sample\USB\Application\cube.exe
fpga\Chapter6 Sample\USB\Application\cube.h
fpga\Chapter6 Sample\USB\Application\cube.mak
fpga\Chapter6 Sample\USB\Application\cube.ncb
fpga\Chapter6 Sample\USB\Application\cube.opt
fpga\Chapter6 Sample\USB\Application\cube.plg
fpga\Chapter6 Sample\USB\Application\cubedoc.cpp
fpga\Chapter6 Sample\USB\Application\cubedoc.h
fpga\Chapter6 Sample\USB\Application\cubeview.cpp
fpga\Chapter6 Sample\USB\Application\cubeview.h
fpga\Chapter6 Sample\USB\Application\mainfrm.cpp
fpga\Chapter6 Sample\USB\Application\mainfrm.h
fpga\Chapter6 Sample\USB\Application\makefile
fpga\Chapter6 Sample\USB\Application\resource.h
fpga\Chapter6 Sample\USB\Application\stdafx.cpp
fpga\Chapter6 Sample\USB\Application\stdafx.h
fpga\Chapter6 Sample\USB\Application\res\cube.ico
fpga\Chapter6 Sample\USB\Application\res\cube.rc2
fpga\Chapter6 Sample\USB\Application\res\toolbar.bmp
fpga\Chapter6 Sample\USB\Driver\USBSoftLock.dsw
fpga\Chapter6 Sample\USB\Driver\USBSoftLock.inf
fpga\Chapter6 Sample\USB\Driver\USBSoftLock.opt
fpga\Chapter6 Sample\USB\Driver\USBSoftLock.sys
fpga\Chapter6 Sample\USB\Driver\USBSoftLockDeviceInterface.h
fpga\Chapter6 Sample\USB\Driver\USBSoftLockioctl.h
fpga\Chapter6 Sample\USB\Driver\dirs
fpga\Chapter6 Sample\USB\Driver\readme.txt
fpga\Chapter6 Sample\USB\Driver\exe\OpenByIntf.cpp
fpga\Chapter6 Sample\USB\Driver\exe\Test_USBSoftLock.cpp
fpga\Chapter6 Sample\USB\Driver\exe\Test_USBSoftLock.dsp
fpga\Chapter6 Sample\USB\Driver\exe\Test_USBSoftLock.plg
fpga\Chapter6 Sample\USB\Driver\exe\Test_USBSoftLock.stc
fpga\Chapter6 Sample\USB\Driver\exe\makefile
fpga\Chapter6 Sample\USB\Driver\exe\sources
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.cpp
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.dsp
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.h
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.inf
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.plg
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.rc
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.stc
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLock.sys
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLockDevice.cpp
fpga\Chapter6 Sample\USB\Driver\sys\USBSoftLockDevice.h
fpga\Chapter6 Sample\USB\Driver\sys\function.h
fpga\Chapter6 Sample\USB\Driver\sys\makefile
fpga\Chapter6 Sample\USB\Driver\sys\resource.h
fpga\Chapter6 Sample\USB\Driver\sys\sources
fpga\Chapter6 Sample\USB\Firmware\DeviceTranseiver.jhd
fpga\Chapter6 Sample\USB\Firmware\DeviceTranseiver.vhd
fpga\Chapter6 Sample\USB\Firmware\EdgeController.jhd
fpga\Chapter6 Sample\USB\Firmware\EdgeController.vhd
fpga\Chapter6 Sample\USB\Firmware\Firmware.npl
fpga\Chapter6 Sample\USB\Firmware\Firmware.ptf
fpga\Chapter6 Sample\USB\Firmware\FrequencyDivider.jhd
fpga\Chapter6 Sample\USB\Firmware\FrequencyDivider.vhd
fpga\Chapter6 Sample\USB\Firmware\IOSwitch.jhd
fpga\Chapter6 Sample\USB\Firmware\IOSwitch.vhd
fpga\Chapter6 Sample\USB\Firmware\PDIUSBD12_Package.vhd
fpga\Chapter6 Sample\USB\Firmware\RequestHandler.jhd
fpga\Chapter6 Sample\USB\Firmware\RequestHandler.vhd
fpga\Chapter6 Sample\USB\Firmware\USBSoftLock.jhd
fpga\Chapter6 Sample\USB\Firmware\USBSoftLock.vhd
fpga\Chapter6 Sample\USB\Firmware\USBSoftLock_ucf.ucf
fpga\Chapter6 Sample\USB\Firmware\USB_Package.vhd
fpga\Chapter6 Sample\USB\Firmware\usbsoftlock_TB.jhd
fpga\Chapter6 Sample\USB\Firmware\usbsoftlock_TB.vhd
fpga\Chapter6 Sample\USB\Firmware\__projnav\runXst_tcl.rsp
fpga\Chapter5 Sample\使用说明.txt
fpga\Chapter5 Sample\UART\UART.npl
fpga\Chapter5 Sample\UART\UART_PACKAGE.vhd
fpga\Chapter5 Sample\UART\baudrate_generator.jhd
fpga\Chapter5 Sample\UART\baudrate_generator.vhd
fpga\Chapter5 Sample\UART\baudrate_generator_TB.jhd
fpga\Chapter5 Sample\UART\baudrate_generator_TB.vhd
fpga\Chapter5 Sample\UART\counter.jhd
fpga\Chapter5 Sample\UART\counter.vhd
fpga\Chapter5 Sample\UART\counter_TB.jhd
fpga\Chapter5 Sample\UART\counter_TB.vhd
fpga\Chapter5 Sample\UART\detector.jhd
fpga\Chapter5 Sample\UART\detector.vhd
fpga\Chapter5 Sample\UART\detector_TB.jhd
fpga\Chapter5 Sample\UART\detector_TB.vhd
fpga\Chapter5 Sample\UART\parity_verifier.jhd
fpga\Chapter5 Sample\UART\parity_verifier.vhd
fpga\Chapter5 Sample\UART\parity_verifier_TB.jhd
fpga\Chapter5 Sample\UART\parity_verifier_TB.vhd
fpga\Chapter5 Sample\UART\shift_register.jhd
fpga\Chapter5 Sample\UART\shift_register.vhd
fpga\Chapter5 Sample\UART\shift_register_TB.jhd
fpga\Chapter5 Sample\UART\shift_register_TB.vhd
fpga\Chapter5 Sample\UART\switch.jhd
fpga\Chapter5 Sample\UART\switch.vhd
fpga\Chapter5 Sample\UART\switch_bus.jhd
fpga\Chapter5 Sample\UART\switch_bus.vhd
fpga\Chapter5 Sample\UART\switch_bus_TB.jhd
fpga\Chapter5 Sample\UART\switch_bus_TB.vhd
fpga\Chapter5 Sample\UART\uart_core.jhd
fpga\Chapter5 Sample\UART\uart_core.vhd
fpga\Chapter5 Sample\UART\uart_top.jhd
fpga\Chapter5 Sample\UART\uart_top.vhd
fpga\Chapter5 Sample\UART\uart_top_tb.jhd
fpga\Chapter5 Sample\UART\uart_top_tb.vhd
fpga\Chapter5 Sample\UART\__projnav\p00p5000.kis
fpga\Chapter5 Sample\UART\__projnav\p00pi000.kis
fpga\Chapter5 Sample\UART\__projnav\p00pl000.kis
fpga\Chapter5 Sample\UART\__projnav\runXst_tcl.rsp
fpga\Chapter4 Sample\使用说明.txt
fpga\Chapter4 Sample\I2C\I2C.dhp
fpga\Chapter4 Sample\I2C\I2C.npl
fpga\Chapter4 Sample\I2C\coregen.prj
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.cmd_log
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.lso
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.ngc
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.ngr
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.prj
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.stx
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.syr
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl.v
fpga\Chapter4 Sample\I2C\i2c_master_bit_ctrl_vhdl.prj
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.cmd_log
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.lso
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.ngc
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.ngr
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.prj
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.stx
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.syr
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl.v
fpga\Chapter4 Sample\I2C\i2c_master_byte_ctrl_vhdl.prj
fpga\Chapter4 Sample\I2C\i2c_master_defines.v
fpga\Chapter4 Sample\I2C\i2c_master_top.cmd_log
fpga\Chapter4 Sample\I2C\i2c_master_top.lso
fpga\Chapter4 Sample\I2C\i2c_master_top.ngc
fpga\Chapter4 Sample\I2C\i2c_master_top.ngr
fpga\Chapter4 Sample\I2C\i2c_master_top.prj
fpga\Chapter4 Sample\I2C\i2c_master_top.stx
fpga\Chapter4 Sample\I2C\i2c_master_top.syr
fpga\Chapter4 Sample\I2C\i2c_master_top.v
fpga\Chapter4 Sample\I2C\i2c_master_top_vhdl.prj
fpga\Chapter4 Sample\I2C\i2c_slave_model.fdo
fpga\Chapter4 Sample\I2C\i2c_slave_model.ndo
fpga\Chapter4 Sample\I2C\i2c_slave_model.udo
fpga\Chapter4 Sample\I2C\i2c_slave_model.v
fpga\Chapter4 Sample\I2C\prjname.lso
fpga\Chapter4 Sample\I2C\timescale.v
fpga\Chapter4 Sample\I2C\transcript
fpga\Chapter4 Sample\I2C\tst_bench_top.v
fpga\Chapter4 Sample\I2C\wb_master_model.v
fpga\Chapter4 Sample\I2C\__projnav\I2C.gfl
fpga\Chapter4 Sample\I2C\__projnav\I2C_flowplus.gfl
fpga\Chapter4 Sample\I2C\__projnav\coregen.rsp
fpga\Chapter4 Sample\I2C\__projnav\i2c_master_bit_ctrl.xst
fpga\Chapter4 Sample\I2C\__projnav\i2c_master_byte_ctrl.xst
fpga\Chapter4 Sample\I2C\__projnav\i2c_master_top.xst
fpga\Chapter4 Sample\I2C\__projnav\runXst_tcl.rsp
fpga\Chapter4 Sample\I2C\__projnav\xst_sprjTOstx_tcl.rsp
fpga\Chapter4 Sample\I2C\work\_info
fpga\Chapter4 Sample\I2C\work\glbl\_primary.dat
fpga\Chapter4 Sample\I2C\work\glbl\_primary.vhd
fpga\Chapter4 Sample\I2C\work\glbl\verilog.asm
fpga\Chapter4 Sample\I2C\work\i2c_slave_model\_primary.dat
fpga\Chapter4 Sample\I2C\work\i2c_slave_model\_primary.vhd
fpga\Chapter4 Sample\I2C\work\i2c_slave_model\verilog.asm
fpga\Chapter4 Sample\I2C\xst\work\hdllib.ref
fpga\Chapter4 Sample\I2C\xst\work\vlg07\i2c_master_bit_ctrl.bin
fpga\Chapter4 Sample\I2C\xst\work\vlg5C\i2c_master_byte_ctrl.bin
fpga\Chapter4 Sample\I2C\xst\work\vlg67\i2c_master_top.bin
fpga\Chapter10 Sample\eth_clockgen.v
fpga\Chapter10 Sample\eth_cop.v
fpga\Chapter10 Sample\eth_crc.v
fpga\Chapter10 Sample\eth_defines.v
fpga\Chapter10 Sample\eth_fifo.v
fpga\Chapter10 Sample\eth_host.v
fpga\Chapter10 Sample\eth_maccontrol.v
fpga\Chapter10 Sample\eth_macstatus.v
fpga\Chapter10 Sample\eth_memory.v
fpga\Chapter10 Sample\eth_miim.v
fpga\Chapter10 Sample\eth_outputcontrol.v
fpga\Chapter10 Sample\eth_phy.v
fpga\Chapter10 Sample\eth_phy_defines.v
fpga\Chapter10 Sample\eth_random.v
fpga\Chapter10 Sample\eth_receivecontrol.v
fpga\Chapter10 Sample\eth_register.v
fpga\Chapter10 Sample\eth_registers.v
fpga\Chapter10 Sample\eth_rxaddrcheck.v
fpga\Chapter10 Sample\eth_rxcounters.v
fpga\Chapter10 Sample\eth_rxethmac.v
fpga\Chapter10 Sample\eth_rxstatem.v
fpga\Chapter10 Sample\eth_shiftreg.v
fpga\Chapter10 Sample\eth_spram_256x32.v
fpga\Chapter10 Sample\eth_top.v
fpga\Chapter10 Sample\eth_transmitcontrol.v
fpga\Chapter10 Sample\eth_txcounters.v
fpga\Chapter10 Sample\eth_txethmac.v
fpga\Chapter10 Sample\eth_txstatem.v
fpga\Chapter10 Sample\eth_wishbone.v
fpga\Chapter10 Sample\tb_cop.v
fpga\Chapter10 Sample\tb_eth_defines.v
fpga\Chapter10 Sample\tb_eth_top.v
fpga\Chapter10 Sample\tb_ethernet.v
fpga\Chapter10 Sample\tb_ethernet_with_cop.v
fpga\Chapter10 Sample\timescale.v
fpga\Chapter10 Sample\wb_bus_mon.v
fpga\Chapter10 Sample\wb_master32.v
fpga\Chapter10 Sample\wb_master_behavioral.v
fpga\Chapter10 Sample\wb_model_defines.v
fpga\Chapter10 Sample\wb_slave_behavioral.v
fpga\Chapter10 Sample\使用说明.txt
fpga\Chapter9 Sample\canbus\xst\work\vlg01
fpga\Chapter9 Sample\canbus\xst\work\vlg1B
fpga\Chapter9 Sample\canbus\xst\work\vlg31
fpga\Chapter9 Sample\canbus\xst\work\vlg42
fpga\Chapter9 Sample\canbus\xst\work\vlg43
fpga\Chapter9 Sample\canbus\xst\work\vlg48
fpga\Chapter9 Sample\canbus\xst\work\vlg49
fpga\Chapter9 Sample\canbus\xst\work\vlg4F
fpga\Chapter9 Sample\canbus\xst\work\vlg5E
fpga\Chapter9 Sample\canbus\xst\work\vlg70
fpga\Chapter8 Sample\vga\xst\work\vlg04
fpga\Chapter8 Sample\vga\xst\work\vlg05
fpga\Chapter8 Sample\vga\xst\work\vlg07
fpga\Chapter8 Sample\vga\xst\work\vlg34
fpga\Chapter8 Sample\vga\xst\work\vlg4D
fpga\Chapter8 Sample\vga\xst\work\vlg53
fpga\Chapter8 Sample\vga\xst\work\vlg59
fpga\Chapter8 Sample\vga\xst\work\vlg5D
fpga\Chapter8 Sample\vga\xst\work\vlg5F
fpga\Chapter8 Sample\vga\xst\work\vlg6A
fpga\Chapter8 Sample\vga\xst\work\vlg7B
fpga\Chapter6 Sample\USB\Driver\exe\Debug
fpga\Chapter4 Sample\I2C\xst\work\vlg07
fpga\Chapter4 Sample\I2C\xst\work\vlg5C
fpga\Chapter4 Sample\I2C\xst\work\vlg67
fpga\Chapter9 Sample\canbus\work\can_acf
fpga\Chapter9 Sample\canbus\work\can_bsp
fpga\Chapter9 Sample\canbus\work\can_btl
fpga\Chapter9 Sample\canbus\work\can_crc
fpga\Chapter9 Sample\canbus\work\can_fifo
fpga\Chapter9 Sample\canbus\work\can_ibo
fpga\Chapter9 Sample\canbus\work\can_register
fpga\Chapter9 Sample\canbus\work\can_register_asyn
fpga\Chapter9 Sample\canbus\work\can_register_asyn_syn
fpga\Chapter9 Sample\canbus\work\can_registers
fpga\Chapter9 Sample\canbus\work\can_testbench
fpga\Chapter9 Sample\canbus\work\can_top
fpga\Chapter9 Sample\canbus\work\glbl
fpga\Chapter9 Sample\canbus\xst\work
fpga\Chapter8 Sample\vga\xst\work
fpga\Chapter6 Sample\USB\Application\res
fpga\Chapter6 Sample\USB\Driver\exe
fpga\Chapter6 Sample\USB\Driver\sys
fpga\Chapter6 Sample\USB\Firmware\__projnav
fpga\Chapter4 Sample\I2C\work\glbl
fpga\Chapter4 Sample\I2C\work\i2c_slave_model
fpga\Chapter4 Sample\I2C\xst\work
fpga\Chapter9 Sample\canbus\__projnav
fpga\Chapter9 Sample\canbus\_ngo
fpga\Chapter9 Sample\canbus\work
fpga\Chapter9 Sample\canbus\xst
fpga\Chapter8 Sample\vga\__projnav
fpga\Chapter8 Sample\vga\xst
fpga\Chapter6 Sample\USB\Application
fpga\Chapter6 Sample\USB\Driver
fpga\Chapter6 Sample\USB\Firmware
fpga\Chapter5 Sample\UART\__projnav
fpga\Chapter4 Sample\I2C\__projnav
fpga\Chapter4 Sample\I2C\work
fpga\Chapter4 Sample\I2C\xst
fpga\Chapter9 Sample\canbus
fpga\Chapter8 Sample\vga
fpga\Chapter6 Sample\USB
fpga\Chapter5 Sample\UART
fpga\Chapter4 Sample\I2C
fpga\Chapter9 Sample
fpga\Chapter8 Sample
fpga\Chapter7 Sample
fpga\Chapter6 Sample
fpga\Chapter5 Sample
fpga\Chapter4 Sample
fpga\Chapter10 Sample
fpga