文件名称:clk_div3
介绍说明－－下载内容均来自于网络，请自行研究使用
vhdl语言写的基数分频器，多平台，通过MODESIM仿真-vhdl language to write the base dividers, multi-platform, through simulation MODESIM
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_div3
........\automake.log
........\clk_div3.cmd_log
........\clk_div3.dhp
........\clk_div3.lso
........\clk_div3.ngc
........\clk_div3.ngr
........\clk_div3.npl
........\clk_div3.prj
........\clk_div3.stx
........\clk_div3.syr
........\clk_div3.vhd
........\clk_div3_tbw.ANT
........\clk_div3_tbw.fdo
........\clk_div3_tbw.tbw
........\clk_div3_tbw.udo
........\clk_div3_tbw.vhw
........\coregen.log
........\coregen.prj
........\pepExtractor.prj
........\results.txt
........\transcript
........\vsim.wlf
........\work
........\....\clk_div3
........\....\........\behavioral.asm
........\....\........\behavioral.dat
........\....\........\_primary.dat
........\....\clk_div3_cfg
........\....\............\_primary.dat
........\....\............\_vhdl.asm
........\....\clk_div3_tbw
........\....\............\testbench_arch.asm
........\....\............\testbench_arch.dat
........\....\............\_primary.dat
........\....\_info
........\xst
........\...\work
........\...\....\hdllib.ref
........\...\....\hdpdeps.ref
........\...\....\sub00
........\...\....\.....\vhpl00.vho
........\...\....\.....\vhpl01.vho
........\__projnav
........\.........\clk_div3.gfl
........\.........\clk_div3.xst
........\.........\clk_div3_flowplus.gfl
........\.........\coregen.rsp
........\.........\hb_cmds
........\.........\runXst_tcl.rsp
........\__projnav.log
........\automake.log
........\clk_div3.cmd_log
........\clk_div3.dhp
........\clk_div3.lso
........\clk_div3.ngc
........\clk_div3.ngr
........\clk_div3.npl
........\clk_div3.prj
........\clk_div3.stx
........\clk_div3.syr
........\clk_div3.vhd
........\clk_div3_tbw.ANT
........\clk_div3_tbw.fdo
........\clk_div3_tbw.tbw
........\clk_div3_tbw.udo
........\clk_div3_tbw.vhw
........\coregen.log
........\coregen.prj
........\pepExtractor.prj
........\results.txt
........\transcript
........\vsim.wlf
........\work
........\....\clk_div3
........\....\........\behavioral.asm
........\....\........\behavioral.dat
........\....\........\_primary.dat
........\....\clk_div3_cfg
........\....\............\_primary.dat
........\....\............\_vhdl.asm
........\....\clk_div3_tbw
........\....\............\testbench_arch.asm
........\....\............\testbench_arch.dat
........\....\............\_primary.dat
........\....\_info
........\xst
........\...\work
........\...\....\hdllib.ref
........\...\....\hdpdeps.ref
........\...\....\sub00
........\...\....\.....\vhpl00.vho
........\...\....\.....\vhpl01.vho
........\__projnav
........\.........\clk_div3.gfl
........\.........\clk_div3.xst
........\.........\clk_div3_flowplus.gfl
........\.........\coregen.rsp
........\.........\hb_cmds
........\.........\runXst_tcl.rsp
........\__projnav.log