文件名称:work
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 128kb
- 下载次数：
- 0次
- 提 供 者：
- 陈*
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
利用verilog实现单片机的反向设计。编程环境为modelsim6.0
(系统自动生成,下载前可以参看下载内容)
下载文件列表
work
....\8051.cr.mti
....\8051.mpf
....\aaa.cr.mti
....\aaa.mpf
....\Acc.v
....\All.v
....\ALU.cr.mti
....\ALU.mpf
....\ALU.v
....\alu_src1_sel.v
....\alu_src2_sel.v
....\alu_src3_sel.v
....\Comp.v
....\cy_select.v
....\decode2_4.v
....\decode2_4.v.bak
....\Decoder.v
....\Defines.v
....\Divide.v
....\Dptr.v
....\ext_addr_sel.v
....\immediate_sel.v
....\IndiAddr.v
....\Make
....\Multiply.v
....\op_select.v
....\Pc.v
....\Port_out.v
....\Psw.v
....\Ram.v
....\ram_rd_sel.v
....\Ram_sel.v
....\ram_wr_sel.v
....\Reg1.v
....\Reg2.v
....\Reg3.v
....\Reg4.v
....\Reg5.v
....\Reg8.v
....\Reg8r.v
....\Rom.v
....\rom_addr_sel.v
....\Sp.v
....\Tb_all.v
....\transcript
....\vish_stacktrace.vstf
....\work
....\....\@indi@addr
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\all
....\....\...\verilog.asm
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\alu_src3_sel
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\divide
....\....\......\verilog.asm
....\....\......\_primary.dat
....\....\......\_primary.vhd
....\....\ext_addr_sel
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\multiply
....\....\........\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\reg1
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg2
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg3
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg4
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg5
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg8
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg8r
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\.....\_primary.vhd
....\8051.cr.mti
....\8051.mpf
....\aaa.cr.mti
....\aaa.mpf
....\Acc.v
....\All.v
....\ALU.cr.mti
....\ALU.mpf
....\ALU.v
....\alu_src1_sel.v
....\alu_src2_sel.v
....\alu_src3_sel.v
....\Comp.v
....\cy_select.v
....\decode2_4.v
....\decode2_4.v.bak
....\Decoder.v
....\Defines.v
....\Divide.v
....\Dptr.v
....\ext_addr_sel.v
....\immediate_sel.v
....\IndiAddr.v
....\Make
....\Multiply.v
....\op_select.v
....\Pc.v
....\Port_out.v
....\Psw.v
....\Ram.v
....\ram_rd_sel.v
....\Ram_sel.v
....\ram_wr_sel.v
....\Reg1.v
....\Reg2.v
....\Reg3.v
....\Reg4.v
....\Reg5.v
....\Reg8.v
....\Reg8r.v
....\Rom.v
....\rom_addr_sel.v
....\Sp.v
....\Tb_all.v
....\transcript
....\vish_stacktrace.vstf
....\work
....\....\@indi@addr
....\....\..........\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\all
....\....\...\verilog.asm
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\alu_src3_sel
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\divide
....\....\......\verilog.asm
....\....\......\_primary.dat
....\....\......\_primary.vhd
....\....\ext_addr_sel
....\....\............\verilog.asm
....\....\............\_primary.dat
....\....\............\_primary.vhd
....\....\multiply
....\....\........\verilog.asm
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\reg1
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg2
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg3
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg4
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg5
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg8
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\reg8r
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\.....\_primary.vhd