文件名称:pcie_ml555x4_prj
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已经在xilinx的ML555开发板上实现的PCIEx4的设计，其中带有DMA功能。满足pciexpress1.0规范。-Already in the Xilinx ML555 development board to achieve PCIEx4 design, which features with DMA. Pciexpress1.0 meet the specification.
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下载文件列表
pcie_ml555x4_prj
................\ml555cg
................\.......\coregen.log
................\.......\endpoint_blk_plus_v1_5
................\.......\......................\doc
................\.......\......................\...\pcie_blk_plus_ds551.pdf
................\.......\......................\...\pcie_blk_plus_gsg343.pdf
................\.......\......................\...\pcie_blk_plus_ug341.pdf
................\.......\......................\example_design
................\.......\......................\..............\BMD.v
................\.......\......................\..............\BMD_64.v
................\.......\......................\..............\BMD_64_RX_ENGINE.v
................\.......\......................\..............\BMD_64_TX_ENGINE.v
................\.......\......................\..............\BMD_EP.v
................\.......\......................\..............\BMD_EP_MEM.v
................\.......\......................\..............\BMD_EP_MEM_ACCESS.v
................\.......\......................\..............\BMD_INTR_CTRL.v
................\.......\......................\..............\BMD_TO_CTRL.v
................\.......\......................\..............\EP_MEM.v
................\.......\......................\..............\pci_exp_4_lane_64b_ep.v
................\.......\......................\..............\pci_exp_64b_app.v
................\.......\......................\..............\xilinx_pci_exp_4_lane_ep.v
................\.......\......................\..............\xilinx_pci_exp_4_lane_ep_product.v
................\.......\......................\..............\xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx50t-ff1136-1.ucf
................\.......\......................\implement
................\.......\......................\.........\coregen.log
................\.......\......................\.........\implement.sh
................\.......\......................\.........\make_ace.sh
................\.......\......................\.........\ml555xcf32p.cfi
................\.......\......................\.........\ml555xcf32p.mcs
................\.......\......................\.........\ml555xcf32p.prm
................\.......\......................\.........\ml555xcf32p.sig
................\.......\......................\.........\ml555_prom.sh
................\.......\......................\.........\novas.rc
................\.......\......................\.........\pcie_ace.cmd
................\.......\......................\.........\pcie_x1_plus_v1_5es_imp.ace
................\.......\......................\.........\results
................\.......\......................\.........\.......\mapped.map
................\.......\......................\.........\.......\mapped.mrp
................\.......\......................\.........\.......\mapped.ncd
................\.......\......................\.........\.......\mapped.pcf
................\.......\......................\.........\.......\netlist.lst
................\.......\......................\.........\.......\routed.bgn
................\.......\......................\.........\.......\routed.bit
................\.......\......................\.........\.......\routed.drc
................\.......\......................\.........\.......\routed.nlf
................\.......\......................\.........\.......\routed.pad
................\.......\......................\.........\.......\routed.par
................\.......\......................\.........\.......\routed.twr
................\.......\......................\.........\.......\routed.unroutes
................\.......\......................\.........\.......\routed.xpi
................\.......\......................\.........\.......\routed_pad.csv
................\.......\......................\.........\.......\routed_pad.txt
................\.......\......................\.........\.......\timing.twr
................\.......\......................\.........\xilinx_pci_exp_4_lane_ep_inc.xst
................\.......\...................
................\ml555cg
................\.......\coregen.log
................\.......\endpoint_blk_plus_v1_5
................\.......\......................\doc
................\.......\......................\...\pcie_blk_plus_ds551.pdf
................\.......\......................\...\pcie_blk_plus_gsg343.pdf
................\.......\......................\...\pcie_blk_plus_ug341.pdf
................\.......\......................\example_design
................\.......\......................\..............\BMD.v
................\.......\......................\..............\BMD_64.v
................\.......\......................\..............\BMD_64_RX_ENGINE.v
................\.......\......................\..............\BMD_64_TX_ENGINE.v
................\.......\......................\..............\BMD_EP.v
................\.......\......................\..............\BMD_EP_MEM.v
................\.......\......................\..............\BMD_EP_MEM_ACCESS.v
................\.......\......................\..............\BMD_INTR_CTRL.v
................\.......\......................\..............\BMD_TO_CTRL.v
................\.......\......................\..............\EP_MEM.v
................\.......\......................\..............\pci_exp_4_lane_64b_ep.v
................\.......\......................\..............\pci_exp_64b_app.v
................\.......\......................\..............\xilinx_pci_exp_4_lane_ep.v
................\.......\......................\..............\xilinx_pci_exp_4_lane_ep_product.v
................\.......\......................\..............\xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx50t-ff1136-1.ucf
................\.......\......................\implement
................\.......\......................\.........\coregen.log
................\.......\......................\.........\implement.sh
................\.......\......................\.........\make_ace.sh
................\.......\......................\.........\ml555xcf32p.cfi
................\.......\......................\.........\ml555xcf32p.mcs
................\.......\......................\.........\ml555xcf32p.prm
................\.......\......................\.........\ml555xcf32p.sig
................\.......\......................\.........\ml555_prom.sh
................\.......\......................\.........\novas.rc
................\.......\......................\.........\pcie_ace.cmd
................\.......\......................\.........\pcie_x1_plus_v1_5es_imp.ace
................\.......\......................\.........\results
................\.......\......................\.........\.......\mapped.map
................\.......\......................\.........\.......\mapped.mrp
................\.......\......................\.........\.......\mapped.ncd
................\.......\......................\.........\.......\mapped.pcf
................\.......\......................\.........\.......\netlist.lst
................\.......\......................\.........\.......\routed.bgn
................\.......\......................\.........\.......\routed.bit
................\.......\......................\.........\.......\routed.drc
................\.......\......................\.........\.......\routed.nlf
................\.......\......................\.........\.......\routed.pad
................\.......\......................\.........\.......\routed.par
................\.......\......................\.........\.......\routed.twr
................\.......\......................\.........\.......\routed.unroutes
................\.......\......................\.........\.......\routed.xpi
................\.......\......................\.........\.......\routed_pad.csv
................\.......\......................\.........\.......\routed_pad.txt
................\.......\......................\.........\.......\timing.twr
................\.......\......................\.........\xilinx_pci_exp_4_lane_ep_inc.xst
................\.......\...................