文件名称:crc_wizard_v1_1
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog写的CRC校验程序 非常不错-Written using Verilog procedures are very good CRC Checksum
(系统自动生成,下载前可以参看下载内容)
下载文件列表
crc_wizard_v1_1
...............\examples
...............\........\crc_sample.vhd
...............\........\frame_check.vhd
...............\........\frame_gen.vhd
...............\readme.txt
...............\src
...............\...\crc_components_pkg.vhd
...............\...\crc_functions_pkg.vhd
...............\...\crc_wizard_v1_1.vhd
...............\...\data_ds_modules.vhd
...............\...\rxcrc.vhd
...............\...\state_machine_rx.vhd
...............\...\state_machine_tx.vhd
...............\...\txcrc.vhd
...............\...\V5CRC.vhd
...............\testbench
...............\.........\llcrc_loop_tb.vhd
...............\.........\modelsim.ini
...............\.........\run_crc_sim.pl
...............\.........\sample_test.do
...............\.........\sample_test.do.bak
...............\.........\sample_wave.do
...............\.........\simprim
...............\.........\.......\_info
...............\.........\unisim
...............\.........\......\_info
...............\.........\vsim.wlf
...............\.........\work
...............\.........\....\crc_components
...............\.........\....\..............\_primary.dat
...............\.........\....\..............\_vhdl.asm
...............\.........\....\crc_functions
...............\.........\....\.............\body.asm
...............\.........\....\.............\body.dat
...............\.........\....\.............\_primary.dat
...............\.........\....\.............\_vhdl.asm
...............\.........\....\data_ds_driv_dst
...............\.........\....\................\data_ds_driv_dst_arch.asm
...............\.........\....\................\data_ds_driv_dst_arch.dat
...............\.........\....\................\_primary.dat
...............\.........\....\frame_check
...............\.........\....\...........\rtl.asm
...............\.........\....\...........\rtl.dat
...............\.........\....\...........\_primary.dat
...............\.........\....\frame_gen
...............\.........\....\.........\rtl.asm
...............\.........\....\.........\rtl.dat
...............\.........\....\.........\_primary.dat
...............\.........\....\llcrc_loop_tb
...............\.........\....\.............\llcrc_loop_tb_arch.asm
...............\.........\....\.............\llcrc_loop_tb_arch.dat
...............\.........\....\.............\_primary.dat
...............\.........\....\rx_crc
...............\.........\....\......\rx_crc_arch.asm
...............\.........\....\......\rx_crc_arch.dat
...............\.........\....\......\_primary.dat
...............\.........\....\state_machine_dst
...............\.........\....\.................\state_machine_dst_arch.asm
...............\.........\....\.................\state_machine_dst_arch.dat
...............\.........\....\.................\_primary.dat
...............\.........\....\state_machine_rx
...............\.........\....\................\state_machine_rx_arch.asm
...............\.........\....\................\state_machine_rx_arch.dat
...............\.........\....\................\_primary.dat
...............\.........\....\tx_crc
...............\.........\....\......\tx_crc_arch.asm
...............\.........\....\......\tx_crc_arch.dat
...............\.........\....\......\_primary.dat
...............\.........\....\v5_crc
...............\.........\....\......\rtl.asm
...............\.........\....\......\rtl.dat
...............\.........\....\......\_primary.dat
...............\.........\....\_info
...............\ucf
...............\...\crc_sample.ucf
...............\ug189.pdf
...............\work
...............\....\_info
...............\....\_temp
...............\examples
...............\........\crc_sample.vhd
...............\........\frame_check.vhd
...............\........\frame_gen.vhd
...............\readme.txt
...............\src
...............\...\crc_components_pkg.vhd
...............\...\crc_functions_pkg.vhd
...............\...\crc_wizard_v1_1.vhd
...............\...\data_ds_modules.vhd
...............\...\rxcrc.vhd
...............\...\state_machine_rx.vhd
...............\...\state_machine_tx.vhd
...............\...\txcrc.vhd
...............\...\V5CRC.vhd
...............\testbench
...............\.........\llcrc_loop_tb.vhd
...............\.........\modelsim.ini
...............\.........\run_crc_sim.pl
...............\.........\sample_test.do
...............\.........\sample_test.do.bak
...............\.........\sample_wave.do
...............\.........\simprim
...............\.........\.......\_info
...............\.........\unisim
...............\.........\......\_info
...............\.........\vsim.wlf
...............\.........\work
...............\.........\....\crc_components
...............\.........\....\..............\_primary.dat
...............\.........\....\..............\_vhdl.asm
...............\.........\....\crc_functions
...............\.........\....\.............\body.asm
...............\.........\....\.............\body.dat
...............\.........\....\.............\_primary.dat
...............\.........\....\.............\_vhdl.asm
...............\.........\....\data_ds_driv_dst
...............\.........\....\................\data_ds_driv_dst_arch.asm
...............\.........\....\................\data_ds_driv_dst_arch.dat
...............\.........\....\................\_primary.dat
...............\.........\....\frame_check
...............\.........\....\...........\rtl.asm
...............\.........\....\...........\rtl.dat
...............\.........\....\...........\_primary.dat
...............\.........\....\frame_gen
...............\.........\....\.........\rtl.asm
...............\.........\....\.........\rtl.dat
...............\.........\....\.........\_primary.dat
...............\.........\....\llcrc_loop_tb
...............\.........\....\.............\llcrc_loop_tb_arch.asm
...............\.........\....\.............\llcrc_loop_tb_arch.dat
...............\.........\....\.............\_primary.dat
...............\.........\....\rx_crc
...............\.........\....\......\rx_crc_arch.asm
...............\.........\....\......\rx_crc_arch.dat
...............\.........\....\......\_primary.dat
...............\.........\....\state_machine_dst
...............\.........\....\.................\state_machine_dst_arch.asm
...............\.........\....\.................\state_machine_dst_arch.dat
...............\.........\....\.................\_primary.dat
...............\.........\....\state_machine_rx
...............\.........\....\................\state_machine_rx_arch.asm
...............\.........\....\................\state_machine_rx_arch.dat
...............\.........\....\................\_primary.dat
...............\.........\....\tx_crc
...............\.........\....\......\tx_crc_arch.asm
...............\.........\....\......\tx_crc_arch.dat
...............\.........\....\......\_primary.dat
...............\.........\....\v5_crc
...............\.........\....\......\rtl.asm
...............\.........\....\......\rtl.dat
...............\.........\....\......\_primary.dat
...............\.........\....\_info
...............\ucf
...............\...\crc_sample.ucf
...............\ug189.pdf
...............\work
...............\....\_info
...............\....\_temp