文件名称:uart_zhiwen
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RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
相关搜索： vhdl
rs232
baud
rate
generator
vhdl
baud
rate
generator
uart
RS232
串口
发送
模块
uart_zhiwen
vhdl
baud
rate
generator
rs232
baud
rate
generator
vhdl
baud
rate
generator
uart
RS232
串口
发送
模块
uart_zhiwen
vhdl
baud
rate
generator
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_zhiwen
...........\.lso
...........\baud_gen.prj
...........\baud_gen.stx
...........\baud_gen.v
...........\baud_gen.xst
...........\baud_gen_vhdl.prj
...........\uart_rx.prj
...........\uart_rx.stx
...........\uart_rx.v
...........\uart_rx.xst
...........\uart_rx_vhdl.prj
...........\uart_top.cmd_log
...........\uart_top.lso
...........\uart_top.prj
...........\uart_top.syr
...........\uart_top.v
...........\uart_top.xst
...........\uart_top_vhdl.prj
...........\uart_tx.prj
...........\uart_tx.stx
...........\uart_tx.v
...........\uart_tx.xst
...........\uart_tx_vhdl.prj
...........\uart_zhiwen.ise
...........\uart_zhiwen.ise_ISE_Backup
...........\xst
...........\...\dump.xst
...........\...\........\uart_top.prj
...........\...\........\............\ngx
...........\...\........\............\...\notopt
...........\...\........\............\...\opt
...........\...\projnav.tmp
...........\...\work
...........\...\....\hdllib.ref
...........\...\....\vlg1A
...........\...\....\.....\uart__top.bin
...........\...\....\vlg21
...........\...\....\.....\uart__rx.bin
...........\...\....\vlg2B
...........\...\....\.....\uart__tx.bin
...........\...\....\vlg59
...........\...\....\.....\baud__gen.bin
...........\_xmsgs
...........\......\xst.xmsgs
...........\.lso
...........\baud_gen.prj
...........\baud_gen.stx
...........\baud_gen.v
...........\baud_gen.xst
...........\baud_gen_vhdl.prj
...........\uart_rx.prj
...........\uart_rx.stx
...........\uart_rx.v
...........\uart_rx.xst
...........\uart_rx_vhdl.prj
...........\uart_top.cmd_log
...........\uart_top.lso
...........\uart_top.prj
...........\uart_top.syr
...........\uart_top.v
...........\uart_top.xst
...........\uart_top_vhdl.prj
...........\uart_tx.prj
...........\uart_tx.stx
...........\uart_tx.v
...........\uart_tx.xst
...........\uart_tx_vhdl.prj
...........\uart_zhiwen.ise
...........\uart_zhiwen.ise_ISE_Backup
...........\xst
...........\...\dump.xst
...........\...\........\uart_top.prj
...........\...\........\............\ngx
...........\...\........\............\...\notopt
...........\...\........\............\...\opt
...........\...\projnav.tmp
...........\...\work
...........\...\....\hdllib.ref
...........\...\....\vlg1A
...........\...\....\.....\uart__top.bin
...........\...\....\vlg21
...........\...\....\.....\uart__rx.bin
...........\...\....\vlg2B
...........\...\....\.....\uart__tx.bin
...........\...\....\vlg59
...........\...\....\.....\baud__gen.bin
...........\_xmsgs
...........\......\xst.xmsgs