文件名称:multicycle

  • 所属分类:
  • 微处理器(ARM/PowerPC等)
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 94kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 孙**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

多周期处理器--verilog写的,欢迎大家来下载,-multicycle microprocessor written with verilog HDL
(系统自动生成,下载前可以参看下载内容)

下载文件列表

multicycle

..........\adder.v

..........\ALU.v

..........\ALU.v.bak

..........\aludec.v

..........\aludec.v.bak

..........\bit32_Processor.v

..........\Controller.v

..........\Controller.v.bak

..........\DataMem.v.bak

..........\Datapath.v

..........\Datapath.v.bak

..........\flopr.v

..........\flopr.v.bak

..........\InsMem.v

..........\InsMem.v.bak

..........\maindec.v

..........\maindec.v.bak

..........\Mem.v

..........\Mem.v.bak

..........\multicycle.cr.mti

..........\multicycle.mpf

..........\mux.v

..........\mux.v.bak

..........\mux3.v

..........\mux3.v.bak

..........\mux4.v

..........\mux4.v.bak

..........\Processor.v

..........\Processor.v.bak

..........\RegFile.v

..........\RegFile.v.bak

..........\signExt.v

..........\SL2.v

..........\top.v

..........\top.v.bak

..........\top_tb.v

..........\top_tb.v.bak

..........\vsim.wlf

..........\work

..........\....\@13432-bit@processor@134

..........\....\........................\verilog.psm

..........\....\........................\_primary.dat

..........\....\........................\_primary.vhd

..........\....\@a@l@u

..........\....\......\verilog.psm

..........\....\......\_primary.dat

..........\....\......\_primary.vhd

..........\....\@data@mem

..........\....\.........\verilog.psm

..........\....\.........\_primary.dat

..........\....\.........\_primary.vhd

..........\....\@ins@mem

..........\....\........\verilog.psm

..........\....\........\_primary.dat

..........\....\........\_primary.vhd

..........\....\@mem

..........\....\....\verilog.psm

..........\....\....\_primary.dat

..........\....\....\_primary.vhd

..........\....\@processor

..........\....\..........\verilog.psm

..........\....\..........\_primary.dat

..........\....\..........\_primary.vhd

..........\....\@s@l2

..........\....\.....\verilog.psm

..........\....\.....\_primary.dat

..........\....\.....\_primary.vhd

..........\....\add

..........\....\...\verilog.psm

..........\....\...\_primary.dat

..........\....\...\_primary.vhd

..........\....\aludec

..........\....\......\verilog.psm

..........\....\......\_primary.dat

..........\....\......\_primary.vhd

..........\....\controller

..........\....\..........\verilog.psm

..........\....\..........\_primary.dat

..........\....\..........\_primary.vhd

..........\....\datapath

..........\....\........\verilog.psm

..........\....\........\_primary.dat

..........\....\........\_primary.vhd

..........\....\flopr

..........\....\.....\verilog.psm

..........\....\.....\_primary.dat

..........\....\.....\_primary.vhd

..........\....\maindec

..........\....\.......\verilog.psm

..........\....\.......\_primary.dat

..........\....\.......\_primary.vhd

..........\....\mux2

..........\....\....\verilog.psm

..........\....\....\_primary.dat

..........\....\....\_primary.vhd

..........\....\mux3

..........\....\....\verilog.psm

..........\....\....\_primary.dat

..........\....\....\_primary.vhd

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