文件名称:USB2.0
介绍说明－－下载内容均来自于网络，请自行研究使用
UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。
-UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
-UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
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下载文件列表
USB2.0
......\USB2.0IP_core_Verilog
......\.....................\usb2.0.txt
......\.....................\USB2.0的IP核，包含文档和Verilog源码
......\.....................\...................................\usb_funct
......\.....................\...................................\.........\bench
......\.....................\...................................\.........\.....\CVS
......\.....................\...................................\.........\.....\...\Entries
......\.....................\...................................\.........\.....\...\Repository
......\.....................\...................................\.........\.....\...\Root
......\.....................\...................................\.........\.....\verilog
......\.....................\...................................\.........\.....\.......\CVS
......\.....................\...................................\.........\.....\.......\...\Entries
......\.....................\...................................\.........\.....\.......\...\Repository
......\.....................\...................................\.........\.....\.......\...\Root
......\.....................\...................................\.........\doc
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\README.txt
......\.....................\...................................\.........\...\STATUS.txt
......\.....................\...................................\.........\...\usb_doc.pdf
......\.....................\...................................\.........\rtl
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\verilog
......\.....................\...................................\.........\...\.......\CVS
......\.....................\...................................\.........\...\.......\...\Entries
......\.....................\...................................\.........\...\.......\...\Repository
......\.....................\...................................\.........\...\.......\...\Root
......\.....................\...................................\.........\...\.......\usbf_crc16.v
......\.....................\...................................\.........\...\.......\usbf_crc5.v
......\.....................\...................................\.........\...\.......\usbf_defines.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf_dummy.v
......\.....................\...................................\.........\...\.......\usbf_idma.v
......\.....................\...................................\.........\...\.......\usbf_mem_arb.v
......\.....................\...................................\.........\...\.......\usbf_pa.v
......\.....................\...................................\.........\...\.......\usbf_pd.v
......\.....................\...................................\.........\...\.......\usbf_pe.v
......\.....................\...................................\.........\...\.......\usbf_pl.v
......\.....................\...................................\.........\...\.......\usbf_rf.v
......\.....................\...................................\.........\...\.......\usbf_top.v
......\.....................\..............
......\USB2.0IP_core_Verilog
......\.....................\usb2.0.txt
......\.....................\USB2.0的IP核，包含文档和Verilog源码
......\.....................\...................................\usb_funct
......\.....................\...................................\.........\bench
......\.....................\...................................\.........\.....\CVS
......\.....................\...................................\.........\.....\...\Entries
......\.....................\...................................\.........\.....\...\Repository
......\.....................\...................................\.........\.....\...\Root
......\.....................\...................................\.........\.....\verilog
......\.....................\...................................\.........\.....\.......\CVS
......\.....................\...................................\.........\.....\.......\...\Entries
......\.....................\...................................\.........\.....\.......\...\Repository
......\.....................\...................................\.........\.....\.......\...\Root
......\.....................\...................................\.........\doc
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\README.txt
......\.....................\...................................\.........\...\STATUS.txt
......\.....................\...................................\.........\...\usb_doc.pdf
......\.....................\...................................\.........\rtl
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\verilog
......\.....................\...................................\.........\...\.......\CVS
......\.....................\...................................\.........\...\.......\...\Entries
......\.....................\...................................\.........\...\.......\...\Repository
......\.....................\...................................\.........\...\.......\...\Root
......\.....................\...................................\.........\...\.......\usbf_crc16.v
......\.....................\...................................\.........\...\.......\usbf_crc5.v
......\.....................\...................................\.........\...\.......\usbf_defines.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf_dummy.v
......\.....................\...................................\.........\...\.......\usbf_idma.v
......\.....................\...................................\.........\...\.......\usbf_mem_arb.v
......\.....................\...................................\.........\...\.......\usbf_pa.v
......\.....................\...................................\.........\...\.......\usbf_pd.v
......\.....................\...................................\.........\...\.......\usbf_pe.v
......\.....................\...................................\.........\...\.......\usbf_pl.v
......\.....................\...................................\.........\...\.......\usbf_rf.v
......\.....................\...................................\.........\...\.......\usbf_top.v
......\.....................\..............