文件名称:Micron_DDR
- 所属分类：
- 其他小程序
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 422kb
- 下载次数：
- 0次
- 提 供 者：
- rober******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Micron_DDR
..........\1024Mb_ddr2
..........\...........\ddr2.v
..........\...........\ddr2_mcp.v
..........\...........\ddr2_module.v
..........\...........\readme.txt
..........\...........\tb.do
..........\...........\tb.v
..........\ddr2_parameters.vh
..........\infor.txt
..........\Micron_ddr.cr.mti
..........\Micron_ddr.mpf
..........\subtest.vh
..........\transcript
..........\vsim.wlf
..........\wave.do
..........\work
..........\....\ddr2
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\ddr2_mcp
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\ddr2_module
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\dqrx
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\tb
..........\....\..\verilog.asm
..........\....\..\_primary.dat
..........\....\..\_primary.vhd
..........\....\_info
..........\....\_opt
..........\....\....\work_ddr2_fast.dt2
..........\....\....\work_dqrx_fast.asm
..........\....\....\work_dqrx_fast.dt2
..........\....\....\work_tb_fast.asm
..........\....\....\work_tb_fast.dt2
..........\....\....\work__info
..........\....\....\_deps
..........\....\_temp
..........\1024Mb_ddr2
..........\...........\ddr2.v
..........\...........\ddr2_mcp.v
..........\...........\ddr2_module.v
..........\...........\readme.txt
..........\...........\tb.do
..........\...........\tb.v
..........\ddr2_parameters.vh
..........\infor.txt
..........\Micron_ddr.cr.mti
..........\Micron_ddr.mpf
..........\subtest.vh
..........\transcript
..........\vsim.wlf
..........\wave.do
..........\work
..........\....\ddr2
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\ddr2_mcp
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\ddr2_module
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\dqrx
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\tb
..........\....\..\verilog.asm
..........\....\..\_primary.dat
..........\....\..\_primary.vhd
..........\....\_info
..........\....\_opt
..........\....\....\work_ddr2_fast.dt2
..........\....\....\work_dqrx_fast.asm
..........\....\....\work_dqrx_fast.dt2
..........\....\....\work_tb_fast.asm
..........\....\....\work_tb_fast.dt2
..........\....\....\work__info
..........\....\....\_deps
..........\....\_temp