verilog hdl教程135例

....................\chap10

....................\......\acc.acf

....................\......\acc.hif

....................\......\acc.v

....................\......\accn.v

....................\......\add8.v

....................\......\adder8.v

....................\......\block1.v

....................\......\block2.v

....................\......\block3.v

....................\......\block4.v

....................\......\control.v

....................\......\fsm.v

....................\......\longframe1.v

....................\......\longframe2.v

....................\......\pipeline.v

....................\......\reg8.v

....................\......\resource1.v

....................\......\resource2.v

....................\......\transcript

....................\chap11

....................\......\account.v

....................\......\clock.v

....................\......\count10.v

....................\......\fre_ctrl.v

....................\......\latch_16.v

....................\......\paobiao.v

....................\......\sell.v

....................\......\song.v

....................\......\traffic.v

....................\chap12

....................\......\add_ahead.v

....................\......\add_ahead1.v

....................\......\add_bx.v

....................\......\add_jl.v

....................\......\add_tree.v

....................\......\correlator.v

....................\......\crc.v

....................\......\cycle.v

....................\......\decoder1.v

....................\......\decoder2.v

....................\......\fir.v

....................\......\linear.v

....................\......\mult.v

....................\......\mult4x4.v

....................\chap3

....................\.....\adder4.acf

....................\.....\adder4.hif

....................\.....\adder4.ndb

....................\.....\adder4.v

....................\.....\adder_tp.v

....................\.....\aoi.v

....................\.....\count4.v

....................\.....\count4_tp.v

....................\.....\transcript

....................\.....\vsim.wlf

....................\.....\work

....................\.....\....\counter

....................\.....\....\.......\verilog.asm

....................\.....\....\.......\_primary.dat

....................\.....\....\.......\_primary.vhd

....................\.....\....\test_counter

....................\.....\....\............\verilog.asm

....................\.....\....\............\_primary.dat

....................\.....\....\............\_primary.vhd

....................\.....\....\_info

....................\chap5

....................\.....\adder.v

....................\.....\adder16.v

....................\.....\alu.v

....................\.....\block.v

....................\.....\buried_ff.v

....................\.....\compile.v

....................\.....\count.v

....................\.....\count60.v

....................\.....\decode4_7.v

....................\.....\loop1.v

....................\.....\loop2.v

....................\.....\loop3.v

....................\.....\mult_for.v

....................\.....\mult_repeat.v

....................\.....\mux21_1.v

....................\.....\mux21_2.v

....................\.....\mux4_1.v

....................\.....\mux_casez.v

....................\.....\non_block.v

....................\.....\test.v

....................\.....\transcript

....................\.....\voter7.v

....................\.....\wave1.v

....................\.....\wave2.v

....................\chap6

....................\.....\alutask.v

....................\.....\alu_tp.v

....................\.....\code_83.v

....................\.....\count.v

....................\.....\funct.v

....................\.....\funct_tp.v

....................\.....\paral1.v