文件名称:2004818105518701
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 3kb
- 下载次数：
- 0次
- 提 供 者：
- t**
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3310液晶显示屏C51测试程序
2004/07/31/BD2YA
接脚资料：
Pin Signal Descr iption Port
1:VDD
Power Input. Logic supply voltage range VDD to GND : 2.7 to 3.3 V
2:SCLK
Serial clock. Input for the clock signal: 0.0 to 4.0 Mbits/s.
3:SDIN
Serial data. Input for the data line.
4:D/C
Mode Select. To select either command/address or data input.
5:SCE
Chip enable input. The enable pin allows data to be clocked in. The signal is active LOW.
6:GND
Ground
7:VOUT
Ouptut voltage. Add external 1-10 uF electrolytic capacitor from VOUT to GND
8:RES
External reset. This signal will reset the device and must be applied to properly
initialize the chip. The signal is active LOW.
控制芯片：
PCD8544 */-3310 LCD screen C51 test procedure information 2004/07/31/BD2YA pin: Pin Signal Descr iption Port 1: VDD Power Input. Logic supply voltage range VDD to GND: 2.7 to 3.3 V 2: SCLK Serial clock. Input for the clock signal: 0.0 to 4.0 Mbits/s. 3: SDIN Serial data. Input for the data line. 4: D/C Mode Select. To select either command/address or data input. 5: SCE Chip enable input. The enable pin allows data to be clocked in. The signal is active LOW. 6: GND Ground 7: VOUT Ouptut voltage. Add external 1-10 uF electrolytic capacitor from VOUT to GND 8: RES External reset. This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW. Controller: PCD8544* /
2004/07/31/BD2YA
接脚资料：
Pin Signal Descr iption Port
1:VDD
Power Input. Logic supply voltage range VDD to GND : 2.7 to 3.3 V
2:SCLK
Serial clock. Input for the clock signal: 0.0 to 4.0 Mbits/s.
3:SDIN
Serial data. Input for the data line.
4:D/C
Mode Select. To select either command/address or data input.
5:SCE
Chip enable input. The enable pin allows data to be clocked in. The signal is active LOW.
6:GND
Ground
7:VOUT
Ouptut voltage. Add external 1-10 uF electrolytic capacitor from VOUT to GND
8:RES
External reset. This signal will reset the device and must be applied to properly
initialize the chip. The signal is active LOW.
控制芯片：
PCD8544 */-3310 LCD screen C51 test procedure information 2004/07/31/BD2YA pin: Pin Signal Descr iption Port 1: VDD Power Input. Logic supply voltage range VDD to GND: 2.7 to 3.3 V 2: SCLK Serial clock. Input for the clock signal: 0.0 to 4.0 Mbits/s. 3: SDIN Serial data. Input for the data line. 4: D/C Mode Select. To select either command/address or data input. 5: SCE Chip enable input. The enable pin allows data to be clocked in. The signal is active LOW. 6: GND Ground 7: VOUT Ouptut voltage. Add external 1-10 uF electrolytic capacitor from VOUT to GND 8: RES External reset. This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW. Controller: PCD8544* /
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