文件名称:i2c

  • 所属分类:
  • 书籍源码
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.27mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • ch***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是一个IIC的接口程序,是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码,很通俗易懂.rar-This is an IIC interface procedures for Xia Wen book " verilog Digital System Design Guide," the source of the IIC, it is easy to understand. Rar
(系统自动生成,下载前可以参看下载内容)

下载文件列表

i2c

...\bench

...\.....\CVS

...\.....\...\Entries

...\.....\...\Repository

...\.....\...\Root

...\.....\verilog

...\.....\.......\CVS

...\.....\.......\...\Entries

...\.....\.......\...\Repository

...\.....\.......\...\Root

...\.....\.......\i2c_slave_model.v

...\.....\.......\i2c_slave_model.v.bak

...\.....\.......\spi_slave_model.v

...\.....\.......\spi_slave_model.v.bak

...\.....\.......\tst_bench_top.v

...\.....\.......\tst_bench_top.v.bak

...\.....\.......\wb_master_model.v

...\.....\.......\wb_master_model.v.bak

...\CVS

...\...\Entries

...\...\Repository

...\...\Root

...\doc

...\...\CVS

...\...\...\Entries

...\...\...\Repository

...\...\...\Root

...\...\i2c_specs.pdf

...\...\src

...\...\...\CVS

...\...\...\...\Entries

...\...\...\...\Repository

...\...\...\...\Root

...\...\...\I2C_specs.doc

...\rtl

...\...\CVS

...\...\...\Entries

...\...\...\Repository

...\...\...\Root

...\...\verilog

...\...\.......\CVS

...\...\.......\...\Entries

...\...\.......\...\Repository

...\...\.......\...\Root

...\...\.......\i2c_master_bit_ctrl.v

...\...\.......\i2c_master_bit_ctrl.v.bak

...\...\.......\i2c_master_byte_ctrl.v

...\...\.......\i2c_master_byte_ctrl.v.bak

...\...\.......\i2c_master_defines.v

...\...\.......\i2c_master_top.v

...\...\.......\i2c_master_top.v.bak

...\...\.......\timescale.v

...\...\vhdl

...\...\....\CVS

...\...\....\...\Entries

...\...\....\...\Repository

...\...\....\...\Root

...\...\....\I2C.VHD

...\...\....\i2c_master_bit_ctrl.vhd

...\...\....\i2c_master_byte_ctrl.vhd

...\...\....\i2c_master_top.vhd

...\...\....\readme

...\...\....\tst_ds1621.vhd

...\sim

...\...\CVS

...\...\...\Entries

...\...\...\Repository

...\...\...\Root

...\...\i2c.cr.mti

...\...\i2c.mpf

...\...\i2c_verilog

...\...\...........\CVS

...\...\...........\...\Entries

...\...\...........\...\Repository

...\...\...........\...\Root

...\...\...........\run

...\...\...........\...\bench.vcd

...\...\...........\...\CVS

...\...\...........\...\...\Entries

...\...\...........\...\...\Repository

...\...\...........\...\...\Root

...\...\...........\...\INCA_libs

...\...\...........\...\.........\CVS

...\...\...........\...\.........\...\Entries

...\...\...........\...\.........\...\Repository

...\...\...........\...\.........\...\Root

...\...\...........\...\ncverilog.key

...\...\...........\...\ncverilog.log

...\...\...........\...\run

...\...\...........\...\waves

...\...\...........\...\.....\CVS

...\...\...........\...\.....\...\Entries

...\...\...........\...\.....\...\Repository

...\...\...........\...\.....\...\Root

...\...\vsim.wlf

...\...\work

...\...\....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e

...\...\....\............................\verilog.asm

...\...\....\............................\_primary.dat

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