文件名称:WatchForLab
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下载文件列表
Watch
.....\7-Segment
.....\.........\DigitTo7Segment.vhd
.....\.........\display_package.vhd
.....\.........\SplitToDigit.vhd
.....\ControlLogic
.....\............\ControlLogic.vhd
.....\............\controllogic_package.vhd
.....\Covertor integer to vector
.....\..........................\convert_package.vhd
.....\..........................\IntToVector.vhd
.....\CPU Architecture Lab 1 Web.pdf
.....\Dual Time Offset
.....\................\DualTimeOffset.vhd
.....\................\DualTimeOffsetFullAddSub.vhd
.....\................\dualtimeoffset_package.vhd
.....\EnableGenerator
.....\...............\ClockEnabler.vhd
.....\...............\clockenabler_package.vhd
.....\FullAdder
.....\.........\BitFullAdder.vhd
.....\.........\bitfulladder_package.vhd
.....\.........\FullAdder.vhd
.....\.........\fulladder_package.vhd
.....\FullSub
.....\.......\BitFullSub.vhd
.....\.......\bitfullsub_package.vhd
.....\.......\FullSub.vhd
.....\.......\fullsub_package.vhd
.....\Integer counter
.....\Integer counter With Update
.....\...........................\counter_update_package.vhd
.....\...........................\IntegerCounterUpdate.vhd
.....\...............\counter_package.vhd
.....\...............\IntegerCounter.vhd
.....\OutputSelector
.....\..............\OutputSelector.vhd
.....\..............\outputselector_package.vhd
.....\PulseSync
.....\.........\PulseSyn.vhd
.....\.........\pulsesync_package.vhd
.....\Read Me.txt
.....\RTC
.....\...\RTC.vhd
.....\...\rtc_package.vhd
.....\StopWatch
.....\.........\StopWatch.vhd
.....\.........\StopWatch_package.vhd
.....\System
.....\......\system_package.vhd
.....\watch.vhd
.....\WatchModelSim.cr.mti
.....\WatchModelSim.mpf
.....\watch_package.vhd
.....\work
.....\....\clockenabler
.....\....\............\arc_clockenabler.dat
.....\....\............\arc_clockenabler.dbs
.....\....\............\arc_clockenabler.prw
.....\....\............\arc_clockenabler.psm
.....\....\............\_primary.dat
.....\....\............\_primary.dbs
.....\....\clockenabler_package
.....\....\....................\_primary.dat
.....\....\....................\_primary.dbs
.....\....\....................\_vhdl.prw
.....\....\....................\_vhdl.psm
.....\....\controllogic
.....\....\............\arc_controllogic.dat
.....\....\............\arc_controllogic.dbs
.....\....\............\arc_controllogic.prw
.....\....\............\arc_controllogic.psm
.....\....\............\_primary.dat
.....\....\............\_primary.dbs
.....\....\controllogic_package
.....\....\....................\_primary.dat
.....\....\....................\_primary.dbs
.....\....\....................\_vhdl.prw
.....\....\....................\_vhdl.psm
.....\....\counter_package
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\...............\_vhdl.prw
.....\....\...............\_vhdl.psm
.....\....\counter_update_package
.....\....\......................\_primary.dat
.....\....\......................\_primary.dbs
.....\....\......................\_vhdl.prw
.....\....\......................\_vhdl.psm
.....\....\digitto7segment
.....\....\...............\arc_digitto7segment.dat
.....\....\...............\arc_digitto7segment.dbs
.....\....\...............\arc_digitto7segment.prw
.....\....\...............\arc_digitto7segment.psm
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\display_package
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\...............\_vhdl.prw
.....\7-Segment
.....\.........\DigitTo7Segment.vhd
.....\.........\display_package.vhd
.....\.........\SplitToDigit.vhd
.....\ControlLogic
.....\............\ControlLogic.vhd
.....\............\controllogic_package.vhd
.....\Covertor integer to vector
.....\..........................\convert_package.vhd
.....\..........................\IntToVector.vhd
.....\CPU Architecture Lab 1 Web.pdf
.....\Dual Time Offset
.....\................\DualTimeOffset.vhd
.....\................\DualTimeOffsetFullAddSub.vhd
.....\................\dualtimeoffset_package.vhd
.....\EnableGenerator
.....\...............\ClockEnabler.vhd
.....\...............\clockenabler_package.vhd
.....\FullAdder
.....\.........\BitFullAdder.vhd
.....\.........\bitfulladder_package.vhd
.....\.........\FullAdder.vhd
.....\.........\fulladder_package.vhd
.....\FullSub
.....\.......\BitFullSub.vhd
.....\.......\bitfullsub_package.vhd
.....\.......\FullSub.vhd
.....\.......\fullsub_package.vhd
.....\Integer counter
.....\Integer counter With Update
.....\...........................\counter_update_package.vhd
.....\...........................\IntegerCounterUpdate.vhd
.....\...............\counter_package.vhd
.....\...............\IntegerCounter.vhd
.....\OutputSelector
.....\..............\OutputSelector.vhd
.....\..............\outputselector_package.vhd
.....\PulseSync
.....\.........\PulseSyn.vhd
.....\.........\pulsesync_package.vhd
.....\Read Me.txt
.....\RTC
.....\...\RTC.vhd
.....\...\rtc_package.vhd
.....\StopWatch
.....\.........\StopWatch.vhd
.....\.........\StopWatch_package.vhd
.....\System
.....\......\system_package.vhd
.....\watch.vhd
.....\WatchModelSim.cr.mti
.....\WatchModelSim.mpf
.....\watch_package.vhd
.....\work
.....\....\clockenabler
.....\....\............\arc_clockenabler.dat
.....\....\............\arc_clockenabler.dbs
.....\....\............\arc_clockenabler.prw
.....\....\............\arc_clockenabler.psm
.....\....\............\_primary.dat
.....\....\............\_primary.dbs
.....\....\clockenabler_package
.....\....\....................\_primary.dat
.....\....\....................\_primary.dbs
.....\....\....................\_vhdl.prw
.....\....\....................\_vhdl.psm
.....\....\controllogic
.....\....\............\arc_controllogic.dat
.....\....\............\arc_controllogic.dbs
.....\....\............\arc_controllogic.prw
.....\....\............\arc_controllogic.psm
.....\....\............\_primary.dat
.....\....\............\_primary.dbs
.....\....\controllogic_package
.....\....\....................\_primary.dat
.....\....\....................\_primary.dbs
.....\....\....................\_vhdl.prw
.....\....\....................\_vhdl.psm
.....\....\counter_package
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\...............\_vhdl.prw
.....\....\...............\_vhdl.psm
.....\....\counter_update_package
.....\....\......................\_primary.dat
.....\....\......................\_primary.dbs
.....\....\......................\_vhdl.prw
.....\....\......................\_vhdl.psm
.....\....\digitto7segment
.....\....\...............\arc_digitto7segment.dat
.....\....\...............\arc_digitto7segment.dbs
.....\....\...............\arc_digitto7segment.prw
.....\....\...............\arc_digitto7segment.psm
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\display_package
.....\....\...............\_primary.dat
.....\....\...............\_primary.dbs
.....\....\...............\_vhdl.prw