文件名称:DCT2
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利用VHDL设计实现了DCT变换，在ISE仿真通过-VHDL designs and implements the use of DCT transform, in the ISE simulation through the
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下载文件列表
DCT2\dct.v
....\dct_cos_table.v
....\dct_mac.v
....\dct_syn.v
....\dct_testbench.v
....\dctu.v
....\dctub.v
....\fdct.v
....\zigzag.v
....\dct_syn_summary.html
....\dct_syn.prj
....\dct_syn.xst
....\dct_syn.cmd_log
....\dct_syn.syr
....\dct_syn.lso
....\DCT.ntrc_log
....\dct_syn.ngr
....\dct_syn.ngc
....\dct_syn.stx
....\dct_syn_prev_built.ngd
....\dct_syn_map.map
....\dct_syn_map.ngm
....\dct_syn.pcf
....\dct_syn_map.ncd
....\dct_syn_map.xrpt
....\dct_syn_map.mrp
....\dct_syn.par
....\dct_syn_par.xrpt
....\dct_syn.ptwx
....\dct_syn_pad.csv
....\dct_syn.pad
....\dct_syn_pad.txt
....\dct_syn.unroutes
....\dct_syn.ncd
....\dct_syn.xpi
....\dct_syn_guide.ncd
....\dct_syn.twx
....\dct_syn.twr
....\dct_syn.ut
....\dct_syn.bgn
....\dct_syn.drc
....\dct_syn.bit
....\dct_syn_usage.xml
....\dct_syn_summary.xml
....\device_usage_statistics.html
....\_impact.cmd
....\_impact.log
....\DCT.ise_ISE_Backup
....\dct_testbench.udo
....\dct_testbench.fdo
....\dct_testbench_wave.fdo
....\transcript
....\vsim.wlf
....\dct_syn_xst.xrpt
....\dct_syn.bld
....\dct_syn_ngdbuild.xrpt
....\dct_syn.ngd
....\dct_testbench.ndo
....\dct_testbench_wave.ndo
....\DCT.restore
....\DCT.ise
....\netgen\translate\dct_syn_translate.nlf
....\......\.........\dct_syn_translate.v
....\_xmsgs\xst.xmsgs
....\......\ngdbuild.xmsgs
....\......\netgen.xmsgs
....\work\_info
....\....\glbl\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\dct_testbench\_primary.vhd
....\....\.............\verilog.asm
....\....\.............\_primary.dat
....\....\fdct\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\dct\_primary.vhd
....\....\...\verilog.asm
....\....\...\_primary.dat
....\....\zigzag\_primary.vhd
....\....\......\verilog.asm
....\....\......\_primary.dat
....\....\dctub\_primary.vhd
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\..._mac\_primary.vhd
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\_ngo\netlist.lst
....\xst\dump.xst\dct_syn.prj\ntrc.scr
....\...\work\hdllib.ref
....\...\....\vlg20\dct__syn.bin
....\...\....\...75\fdct.bin
....\...\....\...27\dct.bin
....\...\....\...1C\zigzag.bin
....\...\....\...7A\dctub.bin
....\...\....\...38\dctu.bin
....\dct_cos_table.v
....\dct_mac.v
....\dct_syn.v
....\dct_testbench.v
....\dctu.v
....\dctub.v
....\fdct.v
....\zigzag.v
....\dct_syn_summary.html
....\dct_syn.prj
....\dct_syn.xst
....\dct_syn.cmd_log
....\dct_syn.syr
....\dct_syn.lso
....\DCT.ntrc_log
....\dct_syn.ngr
....\dct_syn.ngc
....\dct_syn.stx
....\dct_syn_prev_built.ngd
....\dct_syn_map.map
....\dct_syn_map.ngm
....\dct_syn.pcf
....\dct_syn_map.ncd
....\dct_syn_map.xrpt
....\dct_syn_map.mrp
....\dct_syn.par
....\dct_syn_par.xrpt
....\dct_syn.ptwx
....\dct_syn_pad.csv
....\dct_syn.pad
....\dct_syn_pad.txt
....\dct_syn.unroutes
....\dct_syn.ncd
....\dct_syn.xpi
....\dct_syn_guide.ncd
....\dct_syn.twx
....\dct_syn.twr
....\dct_syn.ut
....\dct_syn.bgn
....\dct_syn.drc
....\dct_syn.bit
....\dct_syn_usage.xml
....\dct_syn_summary.xml
....\device_usage_statistics.html
....\_impact.cmd
....\_impact.log
....\DCT.ise_ISE_Backup
....\dct_testbench.udo
....\dct_testbench.fdo
....\dct_testbench_wave.fdo
....\transcript
....\vsim.wlf
....\dct_syn_xst.xrpt
....\dct_syn.bld
....\dct_syn_ngdbuild.xrpt
....\dct_syn.ngd
....\dct_testbench.ndo
....\dct_testbench_wave.ndo
....\DCT.restore
....\DCT.ise
....\netgen\translate\dct_syn_translate.nlf
....\......\.........\dct_syn_translate.v
....\_xmsgs\xst.xmsgs
....\......\ngdbuild.xmsgs
....\......\netgen.xmsgs
....\work\_info
....\....\glbl\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\dct_testbench\_primary.vhd
....\....\.............\verilog.asm
....\....\.............\_primary.dat
....\....\fdct\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\dct\_primary.vhd
....\....\...\verilog.asm
....\....\...\_primary.dat
....\....\zigzag\_primary.vhd
....\....\......\verilog.asm
....\....\......\_primary.dat
....\....\dctub\_primary.vhd
....\....\.....\verilog.asm
....\....\.....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\....\_primary.dat
....\....\..._mac\_primary.vhd
....\....\.......\verilog.asm
....\....\.......\_primary.dat
....\_ngo\netlist.lst
....\xst\dump.xst\dct_syn.prj\ntrc.scr
....\...\work\hdllib.ref
....\...\....\vlg20\dct__syn.bin
....\...\....\...75\fdct.bin
....\...\....\...27\dct.bin
....\...\....\...1C\zigzag.bin
....\...\....\...7A\dctub.bin
....\...\....\...38\dctu.bin