文件名称:51_IP_CORE
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用HDL硬件描述语言写成的MCS51系列单片机IP核，其中包括4位的MCU，内容系4篇硕士论文，其中两个需要用CAJ阅读器打开
-HDL Hardware Descr iption Language with written MCS51 Microcontroller IP core, including 4-bit MCU, the contents of a master' s thesis, Department 4, two of which need to open the CAJ Viewer
-HDL Hardware Descr iption Language with written MCS51 Microcontroller IP core, including 4-bit MCU, the contents of a master' s thesis, Department 4, two of which need to open the CAJ Viewer
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下载文件列表
8位RISCMCUIP核的设计.pdf
MC8051单片机IP核的FPGA实现与应用.pdf
4位MCUVERILOG软核设计.nh
8位MCUIP核的功能仿真与FPGA验证.nh
MC8051单片机IP核的FPGA实现与应用.pdf
4位MCUVERILOG软核设计.nh
8位MCUIP核的功能仿真与FPGA验证.nh