文件名称:fpga_drive_ad7892
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 493kb
- 下载次数：
- 0次
- 提 供 者：
- shu****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
利用FPGA驱动12位的AD7892进行模数变换，并将数据存储到SRAM中。FPGA型号为EP1C3-144。并通过LED将12位AD值显示出来。-The use of FPGA-driven 12-bit AD7892 analog to digital conversion, and data is stored in the SRAM. FPGA model EP1C3-144. Through the LED will be 12-bit AD value is displayed.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fpga_drive_ad7892
.................\ad_control.bsf
.................\ad_control.vhd
.................\db
.................\..\fpga_and_ad.db_info
.................\..\fpga_and_ad.eco.cdb
.................\..\fpga_and_ad.sld_design_entry.sci
.................\fpga_and_ad.asm.rpt
.................\fpga_and_ad.bdf
.................\fpga_and_ad.cdf
.................\fpga_and_ad.done
.................\fpga_and_ad.dpf
.................\fpga_and_ad.fit.rpt
.................\fpga_and_ad.fit.smsg
.................\fpga_and_ad.fit.summary
.................\fpga_and_ad.flow.rpt
.................\fpga_and_ad.map.rpt
.................\fpga_and_ad.map.summary
.................\fpga_and_ad.pin
.................\fpga_and_ad.pof
.................\fpga_and_ad.qpf
.................\fpga_and_ad.qsf
.................\fpga_and_ad.qws
.................\fpga_and_ad.sof
.................\fpga_and_ad.tan.rpt
.................\fpga_and_ad.tan.summary
.................\fpga_and_ad_assignment_defaults.qdf
.................\FPGA_AND_USB_080507修改
.................\.......................\bianliang.vhd
.................\.......................\count.vwf
.................\.......................\Data_to_Usb.bsf
.................\.......................\Data_to_Usb.vhd
.................\.......................\db
.................\.......................\..\FPGA_AND_USB.asm.qmsg
.................\.......................\..\FPGA_AND_USB.cbx.xml
.................\.......................\..\FPGA_AND_USB.cmp.cdb
.................\.......................\..\FPGA_AND_USB.cmp.hdb
.................\.......................\..\FPGA_AND_USB.cmp.kpt
.................\.......................\..\FPGA_AND_USB.cmp.logdb
.................\.......................\..\FPGA_AND_USB.cmp.rdb
.................\.......................\..\FPGA_AND_USB.cmp.tdb
.................\.......................\..\FPGA_AND_USB.cmp0.ddb
.................\.......................\..\FPGA_AND_USB.dbp
.................\.......................\..\FPGA_AND_USB.db_info
.................\.......................\..\FPGA_AND_USB.eco.cdb
.................\.......................\..\FPGA_AND_USB.eds_overflow
.................\.......................\..\FPGA_AND_USB.fit.qmsg
.................\.......................\..\FPGA_AND_USB.hier_info
.................\.......................\..\FPGA_AND_USB.hif
.................\.......................\..\FPGA_AND_USB.map.cdb
.................\.......................\..\FPGA_AND_USB.map.hdb
.................\.......................\..\FPGA_AND_USB.map.logdb
.................\.......................\..\FPGA_AND_USB.map.qmsg
.................\.......................\..\FPGA_AND_USB.pre_map.cdb
.................\.......................\..\FPGA_AND_USB.pre_map.hdb
.................\.......................\..\FPGA_AND_USB.psp
.................\.......................\..\FPGA_AND_USB.rtlv.hdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg.cdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg_swap.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.hdb
.................\.......................\..\FPGA_AND_USB.signalprobe.cdb
.................\.......................\..\FPGA_AND_USB.sim.hdb
.................\.......................\..\FPGA_AND_USB.sim.qmsg
.................\.......................\..\FPGA_AND_USB.sim.rdb
.................\.......................\..\FPGA_AND_USB.sim.vwf
.................\.......................\..\FPGA_AND_USB.sld_design_entry.sci
.................\.......................\..\FPGA_AND_USB.sld_design_entry_dsc.sci
.................\.......................\..\FPGA_AND_USB.syn_hier_info
.................\.......................\..\FPGA_AND_USB.tan.qmsg
.................\.......................\..\wed.zsf
.................\.......................\depthcount.bsf
.................\.......................\depthcount.vhd
.................\.......................\Depth_direction.vhd
.................\.......................\dep
.................\ad_control.bsf
.................\ad_control.vhd
.................\db
.................\..\fpga_and_ad.db_info
.................\..\fpga_and_ad.eco.cdb
.................\..\fpga_and_ad.sld_design_entry.sci
.................\fpga_and_ad.asm.rpt
.................\fpga_and_ad.bdf
.................\fpga_and_ad.cdf
.................\fpga_and_ad.done
.................\fpga_and_ad.dpf
.................\fpga_and_ad.fit.rpt
.................\fpga_and_ad.fit.smsg
.................\fpga_and_ad.fit.summary
.................\fpga_and_ad.flow.rpt
.................\fpga_and_ad.map.rpt
.................\fpga_and_ad.map.summary
.................\fpga_and_ad.pin
.................\fpga_and_ad.pof
.................\fpga_and_ad.qpf
.................\fpga_and_ad.qsf
.................\fpga_and_ad.qws
.................\fpga_and_ad.sof
.................\fpga_and_ad.tan.rpt
.................\fpga_and_ad.tan.summary
.................\fpga_and_ad_assignment_defaults.qdf
.................\FPGA_AND_USB_080507修改
.................\.......................\bianliang.vhd
.................\.......................\count.vwf
.................\.......................\Data_to_Usb.bsf
.................\.......................\Data_to_Usb.vhd
.................\.......................\db
.................\.......................\..\FPGA_AND_USB.asm.qmsg
.................\.......................\..\FPGA_AND_USB.cbx.xml
.................\.......................\..\FPGA_AND_USB.cmp.cdb
.................\.......................\..\FPGA_AND_USB.cmp.hdb
.................\.......................\..\FPGA_AND_USB.cmp.kpt
.................\.......................\..\FPGA_AND_USB.cmp.logdb
.................\.......................\..\FPGA_AND_USB.cmp.rdb
.................\.......................\..\FPGA_AND_USB.cmp.tdb
.................\.......................\..\FPGA_AND_USB.cmp0.ddb
.................\.......................\..\FPGA_AND_USB.dbp
.................\.......................\..\FPGA_AND_USB.db_info
.................\.......................\..\FPGA_AND_USB.eco.cdb
.................\.......................\..\FPGA_AND_USB.eds_overflow
.................\.......................\..\FPGA_AND_USB.fit.qmsg
.................\.......................\..\FPGA_AND_USB.hier_info
.................\.......................\..\FPGA_AND_USB.hif
.................\.......................\..\FPGA_AND_USB.map.cdb
.................\.......................\..\FPGA_AND_USB.map.hdb
.................\.......................\..\FPGA_AND_USB.map.logdb
.................\.......................\..\FPGA_AND_USB.map.qmsg
.................\.......................\..\FPGA_AND_USB.pre_map.cdb
.................\.......................\..\FPGA_AND_USB.pre_map.hdb
.................\.......................\..\FPGA_AND_USB.psp
.................\.......................\..\FPGA_AND_USB.rtlv.hdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg.cdb
.................\.......................\..\FPGA_AND_USB.rtlv_sg_swap.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.cdb
.................\.......................\..\FPGA_AND_USB.sgdiff.hdb
.................\.......................\..\FPGA_AND_USB.signalprobe.cdb
.................\.......................\..\FPGA_AND_USB.sim.hdb
.................\.......................\..\FPGA_AND_USB.sim.qmsg
.................\.......................\..\FPGA_AND_USB.sim.rdb
.................\.......................\..\FPGA_AND_USB.sim.vwf
.................\.......................\..\FPGA_AND_USB.sld_design_entry.sci
.................\.......................\..\FPGA_AND_USB.sld_design_entry_dsc.sci
.................\.......................\..\FPGA_AND_USB.syn_hier_info
.................\.......................\..\FPGA_AND_USB.tan.qmsg
.................\.......................\..\wed.zsf
.................\.......................\depthcount.bsf
.................\.......................\depthcount.vhd
.................\.......................\Depth_direction.vhd
.................\.......................\dep