文件名称:SPI-
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模拟spi驱动flash
SO：串行数据输出脚,在一个读操作的过程中,数据从SO脚移位输出。在时钟的下降沿时数据改变。
SI： 串行数据输入脚,所有的操作码、字节地址和数据从SI脚写入,在时钟的上升沿时数据被锁定。
SCK：串行时钟,控制总线上数据输入和输出的时序。
/CS ：芯片使能信号,当其为高电平时,芯片不被选择,SO脚为高阻态,除非一个内部的写操作正在进行,否则芯片处于待机模式 当引脚为低电平时,芯片处于活动模式,在上电后,在任何操作之前需要CS引脚的一个从高电平到低电平的跳变。
/WP：当WP引脚为低时,芯片禁止写入,但是其他的功能正常。当WP引脚为高电平时,所有的功能都正常。当CS为低时,WP变为低可以中断对芯片的写操作。但是如果内部的写周期已经被初始化后,WP变为低不会对写操作造成影响。
-Analog spi-driven flash
SO: Serial data output pin, in a read operation in the process of shifting the output data from the SO pin. The falling edge of the clock when the data changes.
SI: Serial data input pin, all opcodes, byte addresses, and write data from the SI pin, the rising edge of the clock when the data is locked.
SCK: Serial Clock, control bus data input and output timing.
/ CS: chip enable signal, when it is high, the chip is not selected, SO feet for the high-impedance state, unless an internal write operation is in progress, otherwise the chip is in standby mode when the pin is low, the chip is active mode, power-on after the CS pin is required before any operation of the one from high to low transition.
/ WP: When the WP pin is low, the chip ban writing, but other functions properly. When the WP pin is HIGH, all functions are normal. When CS is low, WP into a low, interrupted write operations on the chip. However, if the internal write cycle has been init
SO：串行数据输出脚,在一个读操作的过程中,数据从SO脚移位输出。在时钟的下降沿时数据改变。
SI： 串行数据输入脚,所有的操作码、字节地址和数据从SI脚写入,在时钟的上升沿时数据被锁定。
SCK：串行时钟,控制总线上数据输入和输出的时序。
/CS ：芯片使能信号,当其为高电平时,芯片不被选择,SO脚为高阻态,除非一个内部的写操作正在进行,否则芯片处于待机模式 当引脚为低电平时,芯片处于活动模式,在上电后,在任何操作之前需要CS引脚的一个从高电平到低电平的跳变。
/WP：当WP引脚为低时,芯片禁止写入,但是其他的功能正常。当WP引脚为高电平时,所有的功能都正常。当CS为低时,WP变为低可以中断对芯片的写操作。但是如果内部的写周期已经被初始化后,WP变为低不会对写操作造成影响。
-Analog spi-driven flash
SO: Serial data output pin, in a read operation in the process of shifting the output data from the SO pin. The falling edge of the clock when the data changes.
SI: Serial data input pin, all opcodes, byte addresses, and write data from the SI pin, the rising edge of the clock when the data is locked.
SCK: Serial Clock, control bus data input and output timing.
/ CS: chip enable signal, when it is high, the chip is not selected, SO feet for the high-impedance state, unless an internal write operation is in progress, otherwise the chip is in standby mode when the pin is low, the chip is active mode, power-on after the CS pin is required before any operation of the one from high to low transition.
/ WP: When the WP pin is low, the chip ban writing, but other functions properly. When the WP pin is HIGH, all functions are normal. When CS is low, WP into a low, interrupted write operations on the chip. However, if the internal write cycle has been init
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模拟SPI协议.doc