文件名称:verilog

  • 所属分类:
  • 书籍源码
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 19.11mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 胡*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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大量verilog例程 详细具体 适合于初学者好好学习 -A large number of detailed and specific for verilog routine learn beginner
相关搜索: verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Verilog HDL程序设计\Chapter-1\adder\adder.cr.mti

...................\.........\.....\adder.mpf

...................\.........\.....\adder.v

...................\.........\.....\adder_testbench.do

...................\.........\.....\adder_testbench.v

...................\.........\.....\chart\图1-3.bmp

...................\.........\.....\.....\图1-4.bmp

...................\.........\.....\.....\图1-5.bmp

...................\.........\.....\.....\图1-6.bmp

...................\.........\.....\.....\图1-7.bmp

...................\.........\.....\.....\图1-8.bmp

...................\.........\.....\transcript

...................\.........\.....\vsim.wlf

...................\.........\.....\work\adder\transcript

...................\.........\.....\....\.....\verilog.txt.asm

...................\.........\.....\....\.....\_primary.dat

...................\.........\.....\....\.....\_primary.vhd

...................\.........\.....\....\....._testbench\verilog.asm

...................\.........\.....\....\...............\_primary.dat

...................\.........\.....\....\...............\_primary.vhd

...................\.........\.....\....\_info

...................\.........0\10.2\chart\图10-12.bmp

...................\..........\....\.....\图10-7.bmp

...................\..........\....\.....\图10-8.bmp

...................\..........\....\.....\图10-9.bmp

...................\..........\....\csc.cr.mti

...................\..........\....\csc.mpf

...................\..........\....\csc_testbench.v

...................\..........\....\rgb2ycrcb.v

...................\..........\....\transcript

...................\..........\....\vsim.wlf

...................\..........\....\wave\csc_testbench.bmp

...................\..........\....\....\rgb2ycrcb.bmp

...................\..........\....\.ork\csc_testbench\verilog.asm

...................\..........\....\....\.............\_primary.dat

...................\..........\....\....\.............\_primary.vhd

...................\..........\....\....\rgb2ycrcb\verilog.asm

...................\..........\....\....\.........\_primary.dat

...................\..........\....\....\.........\_primary.vhd

...................\..........\....\....\_info

...................\..........\...3\chart\图10-18.bmp

...................\..........\....\.....\图10-19.bmp

...................\..........\....\.....\图10-20.bmp

...................\..........\....\.....\图10-22.bmp

...................\..........\....\.....\图10-23.bmp

...................\..........\....\.....\图10-25.bmp

...................\..........\....\.....\图10-28.bmp

...................\..........\....\.....\表10-3.bmp

...................\..........\....\dct.cr.mti

...................\..........\....\dct.mpf

...................\..........\....\dct.v

...................\..........\....\dctu.v

...................\..........\....\dctub.v

...................\..........\....\dct_cos_table.v

...................\..........\....\dct_mac.v

...................\..........\....\dct_syn.v

...................\..........\....\dct_testbench.v

...................\..........\....\fdct.v

...................\..........\....\qnr.cr.mti

...................\..........\....\timescale.v

...................\..........\....\transcript

...................\..........\....\vsim.wlf

...................\..........\....\wave\dct.bmp

...................\..........\....\....\dctu.bmp

...................\..........\....\....\dctub.bmp

...................\..........\....\....\dct_testbench.bmp

...................\..........\....\....\fdct.bmp

...................\..........\....\....\zigzag.bmp

...................\..........\....\.ork\bench_top\verilog.asm

...................\..........\....\....\.........\_primary.dat

...................\..........\....\....\.........\_primary.vhd

...................\..........\....\....\dct\verilog.asm

...................\..........\....\....\...\_primary.dat

...................\..........\....\....\...\_primary.vhd

...................\..........\....\....\...u\verilog.asm

...................\..........\....\....\....\_primary.dat

...................\.......

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