文件名称:Full_parallel_architecture_for_turbo_decoding_of_
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- 2012-11-26
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A full-parallel architecture for turbo decoding, which achieves ultrahigh
data rates when using product codes as error correcting codes, is
proposed. This architecture is able to decode product codes using
binary BCH or m-ary Reed-Solomon component codes. The major
advantage of our architecture is that it enables the memory blocks
between all half-iterations to be removed. Moreover, the latency of the
turbo decoder is strongly reduced. The proposed architecture opens the
way to numerous applications such as optical transmission and data
storage. In particular, the block turbo decoding architecture can
support optical transmission at data rates above 10 Gbit=s.
data rates when using product codes as error correcting codes, is
proposed. This architecture is able to decode product codes using
binary BCH or m-ary Reed-Solomon component codes. The major
advantage of our architecture is that it enables the memory blocks
between all half-iterations to be removed. Moreover, the latency of the
turbo decoder is strongly reduced. The proposed architecture opens the
way to numerous applications such as optical transmission and data
storage. In particular, the block turbo decoding architecture can
support optical transmission at data rates above 10 Gbit=s.
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Full-parallel architecture for turbo decoding of product codes.pdf