文件名称:sap1
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這是用verilog寫的一個簡單的處理器，雖然只具有5個指令，但是可以透過這個範例，來了解到cpu的架構，與如何開發處理器，相信會有很大的啟發。-using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.
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下载文件列表
压缩包 : 61918sap1.rar 列表 sap1\sap1.adf sap1\projlib.cfg sap1\sap1.LIB sap1\compile.cfg sap1\bde.set sap1\0.mgf sap1\1.mgf sap1\3.mgf sap1\sap1.wsp sap1\elaboration.log sap1\compile\contents.lib~ sap1\compile\sap1.opt sap1\compile\sap1.erf sap1\compile\sap1.epr sap1\compile\vcp.mod sap1\compile\vcp.top sap1\compile\mega.dag sap1\compile\mega.elb sap1\compile\mega.dbg sap1\compile\mega.itf sap1\compile\mega.asm sap1\compile\mega.bin sap1\compile\mega.off sap1\compile\mega.mod sap1\compile\sources.sth sap1\compile\wave0.dat sap1\compile\wave1.dat sap1\compile\wave10.dat sap1\compile\wave11.dat sap1\compile\wave12.dat sap1\compile\wave2.dat sap1\compile\wave3.dat sap1\compile\wave4.dat sap1\compile\wave5.dat sap1\compile\wave6.dat sap1\compile\wave7.dat sap1\compile\wave8.dat sap1\compile\wave9.dat sap1\compile sap1\log\console.log sap1\log\find.log sap1\log\compile.log sap1\log\simulation.log sap1\log sap1\src\prom.v sap1\src\SAP_1.v sap1\src\Waveform Editor 1.awf sap1\src\TestBench\SAP_1_TB.v sap1\src\TestBench\SAP_1_TB_runtest.do sap1\src\TestBench\SAP_1_TB_settings.txt sap1\src\TestBench sap1\src sap1