文件名称:rtl
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用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
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下载文件列表
压缩包 : 108229rtl.rar 列表 rtl\verilog\BUGS rtl\verilog\CVS\Entries rtl\verilog\CVS\Repository rtl\verilog\CVS\Root rtl\verilog\CVS rtl\verilog\eth_clockgen.v rtl\verilog\eth_cop.v rtl\verilog\eth_crc.v rtl\verilog\eth_defines.v rtl\verilog\eth_fifo.v rtl\verilog\eth_maccontrol.v rtl\verilog\eth_macstatus.v rtl\verilog\eth_miim.v rtl\verilog\eth_outputcontrol.v rtl\verilog\eth_random.v rtl\verilog\eth_receivecontrol.v rtl\verilog\eth_register.v rtl\verilog\eth_registers.v rtl\verilog\eth_rxaddrcheck.v rtl\verilog\eth_rxcounters.v rtl\verilog\eth_rxethmac.v rtl\verilog\eth_rxstatem.v rtl\verilog\eth_shiftreg.v rtl\verilog\eth_spram_256x32.v rtl\verilog\eth_top.v rtl\verilog\eth_transmitcontrol.v rtl\verilog\eth_txcounters.v rtl\verilog\eth_txethmac.v rtl\verilog\eth_txstatem.v rtl\verilog\eth_wishbone.v rtl\verilog\timescale.v rtl\verilog\TODO rtl\verilog\transcript rtl\verilog\xilinx_dist_ram_16x32.v rtl\verilog rtl