文件名称:adis16350_all
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [LabVIEW]
- 上传时间：
- 2012-11-26
- 文件大小：
- 786kb
- 下载次数：
- 0次
- 提 供 者：
- zha0****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
This document outlines how to use the Analog Device ADIS16350 High Precision Tri-Axis Inertial Sensor Evaluation Board with the LabVIEW FPGA implementation of the SPI (Serial Peripheral Interface) digital communication protocol. This example reads and displays graphically the acceleration, angular rate and temperature along three axis
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下载文件列表
ADIS16350_All
.............\ADI16350 RT with FPGA Example
.............\.............................\ADIS16350
.............\.............................\.........\ADIS16350_configuration.vi
.............\.............................\.........\ADIS16350_convert_bin_to_real.vi
.............\.............................\.........\ADIS16350_read_pipeline.vi
.............\.............................\.........\ADIS16350_read_write_single_point.vi
.............\.............................\.........\ADIS16350_sign_extend_16.vi
.............\.............................\cRIO_ADIS16350_Example.aliases
.............\.............................\cRIO_ADIS16350_Example.lvlps
.............\.............................\cRIO_ADIS16350_Example.lvproj
.............\.............................\Example_cRIO_Host.vi
.............\.............................\Example_cRIO_Main.vi
.............\.............................\Example_Port Code_cRIO.vi
.............\.............................\FPGA Bitfiles
.............\.............................\.............\cRIO_ADIS16003_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_adis16060_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_ADIS16250_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_ADIS16350_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\FPGA
.............\....\Code
.............\....\....\FPGA SPI_Globals.vi
.............\....\Controls
.............\....\........\FPGA SPI_Arb Loop State.ctl
.............\....\........\FPGA SPI_Cmd.ctl
.............\....\........\FPGA SPI_Port Loop State.ctl
.............\....\........\FPGA SPI_SPI Loop State.ctl
.............\Host API
.............\........\Controls
.............\........\........\FPGA SPI_FPGA Ref.ctl
.............\........\........\FPGA SPI_SPI Configuration Cluster.ctl
.............\........\FPGA SPI_Configure.vi
.............\........\FPGA SPI_Write Read.vi
.............\........\FPGA_Ready.vi
.............\ADI16350 RT with FPGA Example
.............\.............................\ADIS16350
.............\.............................\.........\ADIS16350_configuration.vi
.............\.............................\.........\ADIS16350_convert_bin_to_real.vi
.............\.............................\.........\ADIS16350_read_pipeline.vi
.............\.............................\.........\ADIS16350_read_write_single_point.vi
.............\.............................\.........\ADIS16350_sign_extend_16.vi
.............\.............................\cRIO_ADIS16350_Example.aliases
.............\.............................\cRIO_ADIS16350_Example.lvlps
.............\.............................\cRIO_ADIS16350_Example.lvproj
.............\.............................\Example_cRIO_Host.vi
.............\.............................\Example_cRIO_Main.vi
.............\.............................\Example_Port Code_cRIO.vi
.............\.............................\FPGA Bitfiles
.............\.............................\.............\cRIO_ADIS16003_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_adis16060_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_ADIS16250_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\.............................\.............\cRIO_ADIS16350_Exa~3C_FPGA Target_Example_cRIO_Main.vi.lvbit
.............\FPGA
.............\....\Code
.............\....\....\FPGA SPI_Globals.vi
.............\....\Controls
.............\....\........\FPGA SPI_Arb Loop State.ctl
.............\....\........\FPGA SPI_Cmd.ctl
.............\....\........\FPGA SPI_Port Loop State.ctl
.............\....\........\FPGA SPI_SPI Loop State.ctl
.............\Host API
.............\........\Controls
.............\........\........\FPGA SPI_FPGA Ref.ctl
.............\........\........\FPGA SPI_SPI Configuration Cluster.ctl
.............\........\FPGA SPI_Configure.vi
.............\........\FPGA SPI_Write Read.vi
.............\........\FPGA_Ready.vi