文件名称:dice-game
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dice game in vhdl program, perform in hex and control by switch in kit FPGA alterna De1
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下载文件列表
dice game
.........\bo_chia_tan.vhd
.........\bo_chia_tan.vhd.bak
.........\bo_cong.vhd
.........\bo_cong.vhd.bak
.........\conv_50Mhz_1Hz.vhd
.........\counter.vhd
.........\counter.vhd.bak
.........\counter1.vhd
.........\counter1.vhd.bak
.........\counter2.vhd
.........\counter2.vhd.bak
.........\db
.........\..\logic_util_heursitic.dat
.........\..\mux_3nc.tdf
.........\..\mux_joc.tdf
.........\..\mux_t4d.tdf
.........\..\mux_umc.tdf
.........\..\prev_cmp_test.asm.qmsg
.........\..\prev_cmp_test.fit.qmsg
.........\..\prev_cmp_test.map.qmsg
.........\..\prev_cmp_test.qmsg
.........\..\prev_cmp_test.sim.qmsg
.........\..\prev_cmp_test.tan.qmsg
.........\..\test.asm.qmsg
.........\..\test.asm.rdb
.........\..\test.cbx.xml
.........\..\test.cmp.bpm
.........\..\test.cmp.cdb
.........\..\test.cmp.ecobp
.........\..\test.cmp.hdb
.........\..\test.cmp.kpt
.........\..\test.cmp.logdb
.........\..\test.cmp.rdb
.........\..\test.cmp.tdb
.........\..\test.cmp0.ddb
.........\..\test.cmp_merge.kpt
.........\..\test.db_info
.........\..\test.eco.cdb
.........\..\test.eds_overflow
.........\..\test.fit.qmsg
.........\..\test.fnsim.cdb
.........\..\test.fnsim.hdb
.........\..\test.fnsim.qmsg
.........\..\test.hier_info
.........\..\test.hif
.........\..\test.lpc.html
.........\..\test.lpc.rdb
.........\..\test.lpc.txt
.........\..\test.map.bpm
.........\..\test.map.cdb
.........\..\test.map.ecobp
.........\..\test.map.hdb
.........\..\test.map.kpt
.........\..\test.map.logdb
.........\..\test.map.qmsg
.........\..\test.map_bb.cdb
.........\..\test.map_bb.hdb
.........\..\test.map_bb.logdb
.........\..\test.pre_map.cdb
.........\..\test.pre_map.hdb
.........\..\test.rtlv.hdb
.........\..\test.rtlv_sg.cdb
.........\..\test.rtlv_sg_swap.cdb
.........\..\test.sgdiff.cdb
.........\..\test.sgdiff.hdb
.........\..\test.sim.cvwf
.........\..\test.sim.hdb
.........\..\test.sim.qmsg
.........\..\test.simfam
.........\..\test.sld_design_entry.sci
.........\..\test.sld_design_entry_dsc.sci
.........\..\test.smart_action.txt
.........\..\test.smp_dump.txt
.........\..\test.syn_hier_info
.........\..\test.tan.qmsg
.........\..\test.tis_db_list.ddb
.........\..\test.tmw_info
.........\..\wed.wsf
.........\dice_test_step.vhd
.........\Digital Systems Design Using VHDL - Charles H. Roth.pdf
.........\fsm.vhd
.........\fsm.vhd.bak
.........\hex.vhd
.........\hex.vhd.bak
.........\hex_1_to_9_1.vhd
.........\hex_2leds.vhd
.........\hex_tong.vhd
.........\hex_tong.vhd.bak
.........\h瓢峄沶g d岷玭 s峄?d峄
.........\bo_chia_tan.vhd
.........\bo_chia_tan.vhd.bak
.........\bo_cong.vhd
.........\bo_cong.vhd.bak
.........\conv_50Mhz_1Hz.vhd
.........\counter.vhd
.........\counter.vhd.bak
.........\counter1.vhd
.........\counter1.vhd.bak
.........\counter2.vhd
.........\counter2.vhd.bak
.........\db
.........\..\logic_util_heursitic.dat
.........\..\mux_3nc.tdf
.........\..\mux_joc.tdf
.........\..\mux_t4d.tdf
.........\..\mux_umc.tdf
.........\..\prev_cmp_test.asm.qmsg
.........\..\prev_cmp_test.fit.qmsg
.........\..\prev_cmp_test.map.qmsg
.........\..\prev_cmp_test.qmsg
.........\..\prev_cmp_test.sim.qmsg
.........\..\prev_cmp_test.tan.qmsg
.........\..\test.asm.qmsg
.........\..\test.asm.rdb
.........\..\test.cbx.xml
.........\..\test.cmp.bpm
.........\..\test.cmp.cdb
.........\..\test.cmp.ecobp
.........\..\test.cmp.hdb
.........\..\test.cmp.kpt
.........\..\test.cmp.logdb
.........\..\test.cmp.rdb
.........\..\test.cmp.tdb
.........\..\test.cmp0.ddb
.........\..\test.cmp_merge.kpt
.........\..\test.db_info
.........\..\test.eco.cdb
.........\..\test.eds_overflow
.........\..\test.fit.qmsg
.........\..\test.fnsim.cdb
.........\..\test.fnsim.hdb
.........\..\test.fnsim.qmsg
.........\..\test.hier_info
.........\..\test.hif
.........\..\test.lpc.html
.........\..\test.lpc.rdb
.........\..\test.lpc.txt
.........\..\test.map.bpm
.........\..\test.map.cdb
.........\..\test.map.ecobp
.........\..\test.map.hdb
.........\..\test.map.kpt
.........\..\test.map.logdb
.........\..\test.map.qmsg
.........\..\test.map_bb.cdb
.........\..\test.map_bb.hdb
.........\..\test.map_bb.logdb
.........\..\test.pre_map.cdb
.........\..\test.pre_map.hdb
.........\..\test.rtlv.hdb
.........\..\test.rtlv_sg.cdb
.........\..\test.rtlv_sg_swap.cdb
.........\..\test.sgdiff.cdb
.........\..\test.sgdiff.hdb
.........\..\test.sim.cvwf
.........\..\test.sim.hdb
.........\..\test.sim.qmsg
.........\..\test.simfam
.........\..\test.sld_design_entry.sci
.........\..\test.sld_design_entry_dsc.sci
.........\..\test.smart_action.txt
.........\..\test.smp_dump.txt
.........\..\test.syn_hier_info
.........\..\test.tan.qmsg
.........\..\test.tis_db_list.ddb
.........\..\test.tmw_info
.........\..\wed.wsf
.........\dice_test_step.vhd
.........\Digital Systems Design Using VHDL - Charles H. Roth.pdf
.........\fsm.vhd
.........\fsm.vhd.bak
.........\hex.vhd
.........\hex.vhd.bak
.........\hex_1_to_9_1.vhd
.........\hex_2leds.vhd
.........\hex_tong.vhd
.........\hex_tong.vhd.bak
.........\h瓢峄沶g d岷玭 s峄?d峄