文件名称:IC-design-examples
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 508kb
- 下载次数：
- 0次
- 提 供 者：
- zcf***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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精通VerilogHDL：IC设计核心技术实例详解 源代码 可以参考-Proficient VerilogHDL: IC the design core technology instance Detailed source code can reference
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下载文件列表
精通VerilogHDL：IC设计核心技术实例详解\部分习题答案.doc
......................................\EX3_3.bmp
......................................\EX3_4.bmp
......................................\习题.vsd
......................................\部分习题源码\ex2_2\demux.fsdb
......................................\............\.....\rtl_wrk\ex2_2\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\ex2_2
......................................\............\.....\.......\_info
......................................\............\.....\rtl_wrk
......................................\............\.....\ex2_2.v
......................................\............\.....\run.do
......................................\............\ex2_2
......................................\............\....3\ex2_3.fsdb
......................................\............\.....\rtl_wrk\ex2_3\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\ex2_3
......................................\............\.....\.......\_info
......................................\............\.....\rtl_wrk
......................................\............\.....\ex2_3.v
......................................\............\.....\ex2_3.v.bak
......................................\............\.....\run.do
......................................\............\ex2_3
......................................\............\....6\ex2_6.fsdb
......................................\............\.....\rtl_wrk\ex2_6\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\ex2_6
......................................\............\.....\.......\_info
......................................\............\.....\rtl_wrk
......................................\............\.....\ex2_6.v
......................................\............\.....\run.do
......................................\............\ex2_6
......................................\............\..3_3\rev_1\syntmp
......................................\............\.....\.....\dff.srr
......................................\............\.....\rev_1
......................................\............\.....\dff.prd
......................................\............\.....\dff.prj
......................................\............\.....\dff.v
......................................\............\ex3_3
......................................\............\..6_1\rtl_wrk\ex6_1\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\ex6_1
......................................\............\.....\.......\comp4\verilog.asm
......................................\............\.....\.......\.....\_primary.dat
......................................\............\.....\.......\.....\_primary.vhd
......................................\............\.....\.......\comp4
......................................\............\.....\.......\....\verilog.asm
......................................\............\.....\.......\....\_primary.dat
......................................\............\.....\.......\....\_primary.vhd
......................................\............\.....\.......\comp
......................................\............\.....\.......\_info
......................................\............\.....\rtl_wrk
......................................\............\.....\comp.v
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