文件名称:leg_source
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verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
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压缩包 : 27796718leg_source.zip 列表 leg_source/ leg_source/inst_code.txt leg_source/leg.v leg_source/leg_dcache.v leg_source/leg_define.v leg_source/leg_dpram_syn.v leg_source/leg_icache.v leg_source/leg_mem_arbitor.v leg_source/leg_mult.v leg_source/leg_rf.v leg_source/leg_shifter.v leg_source/leg_soc.v leg_source/leg_soc_tb.v leg_source/leg_tb.v leg_source/stack_test.cr.mti leg_source/stack_test.mpf leg_source/trace.txt leg_source/work/ leg_source/Workbook of LEG.pdf leg_source/work/leg/ leg_source/work/leg/verilog.asm leg_source/work/leg/_primary.dat leg_source/work/leg/_primary.vhd leg_source/work/leg_dcache/ leg_source/work/leg_dcache/verilog.asm leg_source/work/leg_dcache/_primary.dat leg_source/work/leg_dcache/_primary.vhd leg_source/work/leg_dpram_syn/ leg_source/work/leg_dpram_syn/verilog.asm leg_source/work/leg_dpram_syn/_primary.dat leg_source/work/leg_dpram_syn/_primary.vhd leg_source/work/leg_icache/ leg_source/work/leg_icache/verilog.asm leg_source/work/leg_icache/_primary.dat leg_source/work/leg_icache/_primary.vhd leg_source/work/leg_mem/ leg_source/work/leg_mem/verilog.asm leg_source/work/leg_mem/_primary.dat leg_source/work/leg_mem/_primary.vhd leg_source/work/leg_mult/ leg_source/work/leg_mult/verilog.asm leg_source/work/leg_mult/_primary.dat leg_source/work/leg_mult/_primary.vhd leg_source/work/leg_rf/ leg_source/work/leg_rf/verilog.asm leg_source/work/leg_rf/_primary.dat leg_source/work/leg_rf/_primary.vhd leg_source/work/leg_shifter/ leg_source/work/leg_shifter/verilog.asm leg_source/work/leg_shifter/_primary.dat leg_source/work/leg_shifter/_primary.vhd leg_source/work/leg_tb/ leg_source/work/leg_tb/verilog.asm leg_source/work/leg_tb/_primary.dat leg_source/work/leg_tb/_primary.vhd leg_source/work/_info